Nowadays, FPGAs are large enough to host entire system-on-chip designs, wherein a soft core processor is often an integral part. High performance of the processor is always desirable, so there is an interest in finding faster solutions.This report aims to describe the work and results performed by Karl Bengtson and Olof Andersson at ISY. The task was to continue the development of a soft core microprocessor, originally created by Andreas Ehliar. The first step was to decide a more widely adopted instruction set for the processor. The choice fell upon the MIPS32 instruction set. The main work of the project has been focused on implementing support for MIPS32, allowing the processor to execute MIPS assembly language programs. The development has been done with speed optimization in mind. For every new function, the effects on the maximum frequency has been considered, and solutions not satisfying the speed requirements has been abandoned or revised.The performance has been measured by running a benchmark program—Coremark. Comparison has also been made to the main competitors among soft core processors. The results were positive, and reported a higher Coremark score than the other processors inthe study. The processor described herein still lacks many essential features. Nevertheless, the conclusion is that it may be possible to create a competitive alternative to established soft processors. / FPGAer används idag ofta för stora inbyggda system, i vilka en mjuk processor ofta spelar en viktig roll. Hög prestanda hos processorn är alltid önskvärt, så det finns ett intresse i att hitta snabbare lösningar. Denna rapport skall beskriva det arbete och de resultat som uppnåtts av Karl Bengtson och Olof Andersson på ISY. Uppgiften var att fortsätta utvecklandet av en mjuk processor, som ursprungligen skapats av Andreas Ehliar. Första steget var att välja ut en mer allmänt använd instruktionsuppsättning för processorn. Valet föll på instruktionsuppsättningsarkitekturen MIPS32. Projektets huvutarbete har varit fokuserat på att implementera stöd för MIPS32, vilket ger processorn möjlighet att köra assemblerprogram för MIPS.Utvecklingen har gjorts med hastighetsoptimering i beaktning. För varje ny funktion har dess effekter på maxfrekvensen undersökts,och lösningar som inte uppfyllt hastighetskraven har förkastats eller reviderats. Prestandan har mätts med programmet Coremark. Det har också gjorts jämförelser med huvudkonkurrenterna bland mjuka processorer. Resultaten var positiva, och rapporterade ett högre Coremarkpoäng än de andra processorerna i studien. Slutsatsen är att det ärmöjligt att skapa ett alternativ till de etablerade mjuka processorerna, men att denna processor fortfarande saknar väsentliga funktioner som behövs för att utgöra en mogen produkt.

Tato práce se zabývá problematikou optických bezkabelových spojů (FSO). V úvodní kapitole jsou diskutovány přednosti, základní principy a dílčí komponenty FSO spojů. Druhá kapitola se zabývá atmosférou z pohledu šířícího se optického svazku, jejím složením, základními veličinami a jevy v ní nastávajícími. V následující kapitole je popsáno několik metod ke zmírnění jevů majících negativní vliv na kvalitu spoje. Druhá část práce se zabývá návrhem podpůrného systému pro FSO, založeném na softcore mikroprocesoru MicroBlaze, návrhem jednoduchého síťového přepínače a síťového rozhraní. Závěr práce pojednává o implementaci webového serveru a tvorbě webové prezentace umožňující vzdálenou správu FSO a jeho komponent.

It is widely recognised that security is a concern in the design of a wide range of embedded systems. However, security for embedded systems remains an unsolved problem, which could create greater challenges in the future than security for mainstream computers today. The promise of universal connectivity for embedded systems creates increased possibilities for malicious users to gain unauthorised access to sensitive information. All modern security protocols use private-key and public-key algorithms. This thesis investigates three important cryptography algorithms (RC4, AES, and RSA) and their relevance to networked embedded systems. Limitations in processing power, battery life, communication bandwidth, memory and costs constrain the applicability of existing cryptography standards for small embedded devices. A mismatch between wide arithmetic for security (32 bit word operations) and embedded data bus widths (often only 8 or 16 bits) combined with a lack of certain operations (e. g., multi precision arithmetic) highlight a gap in the domain of networked embedded systems security. The aim of this thesis is to find feasible security solutions for networked embedded system applications. The above mentioned cryptography algorithms have been ported to three hardware platforms (Rabbit RCM3000, Xilinx Virtex 4 FPGA with MicroBlaze softcore, and a Linux desktop machine) in order to simulate several real world scenarios. Three applications – bidirectional transmission with encryption and decryption for various payload length, unidirectional transmission with very short payload, and encrypted data streaming – were developed to meet the simulation requirements. Several timing results were collected and used for calculating the achieved throughput. The Rabbit hardware platform, which represents the lower end in this thesis, was able to perform the RC4 crypto algorithm with a throughput of about 155 kbit/s. Thus the RC4 crypto algorithm was proven to outperform the AES crypto algorithm by a factor of 5, with AES achieving a throughput of about 32 kbit/s with the same hardware platform. The throughput was similar with the streaming application and UDP data transport. Without performing a cryto algorithm, the streaming application was able to process up to 1.5 Mbit/s. RSA was not implemented on the Rabbit hardware platform. The MicroBlaze hardware platform outperformed the Rabbit system by a factor of 5 – 10. It reached a throughput up to 1.5 Mbit/s with RC4 and up to 130 kbit/s with AES. The RSA algorithm reached up to 0.8 kbit/s on this hardware platform, showing that public-key ciphers are only suitable for short payload data, such as the exchange of a session key. The Linux machine was included in this test only to provide a reference to a non embedded system. The Linux performance was better than the MicroBlaze system by a factor of between 67 – 770, and better than the Rabbit platform by a factor of between 645 – 3125. Both the RC4 and the AES crypto algorithm reached a throughput of up to 100 Mbit/s on the Linux machine, with a throughput of up to 130 kbit/s reached with RSA. Hence, the Rabbit platform combined with the RC4 algorithm is suitable, for example, for MP3 streams with up to 150 kbit/s. The Rabbit platform with the AES algorithm could be used for low quality audio streams, for example for speech announcements. If a higher throughput is required, for example for video streams, the MicroBlaze could be an appropriate platform with throughput of up to 1.5 Mbit/s. Low cost embedded systems like Atmel AVR are not suitable for processing cipher algorithms developed in C. It is widely recommended that assembly language is used to develop such platforms.

Στην παρούσα διπλωματική αναπτύσσεται ένα ενσωματωμένο σύστημα αποτελούμενο από υλικό και λογισμικό, για τον χαρακτηρισμό τηλεπικοινωνιακών διατάξεων. Ειδικότερα μελετάται ο έλεγχος εξειδικευμένης ενσωματωμένης τηλεπικοινωνιακής διάταξης, η αυτοματοποίηση της συλλογής δεδομένων ενδιαφέροντος κατά τη λειτουργία της τηλεπικοινωνιακής διάταξης, καθώς και ο τρόπος επικοινωνίας με το χρήστη αναπτυξιακών συστημάτων που βασίζονται σε FPGA και χρησιμοποιούνται για την κατασκευή προτύπων τηλεπικοινωνιακών διατάξεων. Συγκεκριμένα μελετώνται διαφορετικές τεχνικές εισαγωγής και εξαγωγής δεδομένων από τα FPGAs και αποθήκευσής τους σε σύστημα host. O τρόπος εισαγωγής δεδομένων και παραμέτρων στα υπάρχοντα συστήματα παρουσιάζει συγκεκριμένους περιορισμούς. Εδώ μελετάται ο τρόπος που μπορούν τα δεδομένα και παράμετροι να εισάγονται δυναμικά μέσω ενός φιλικού προς τον χρήστη περιβάλλοντος. Επίσης μελετάται ο τρόπος αυτόματης συλλογής όγκου δεδομένων ενδιαφέροντος και εξαγωγής δεδομένων με ασφαλή και αυτοματοποιημένο τρόπο. Για να επιτευχθεί αυτό αναπτύσσεται ένα ενσωματωμένο σύστημα που η διεπαφή χρήστη γίνεται μέσω web server. Η ανάπτυξη περιλαμβάνει τη χρήση ενσωματωμένου επεξεργαστή διαθέσιμου ως IP block σε FPGA, τη δόμηση ενός συστήματος βασισμένου σε κανάλια επικοινωνίας με χρήση εικονικής διευθυνσιοδότησης, καθώς και τον έλεγχο και σύνδεση της μονάδας προτυποποίησης τηλεπικοινωνιακών διατάξεων με το κανάλι επικοινωνίας του επεξεργαστή. Το σύστημα που προκύπτει είναι ένα ενσωματωμένο σύστημα στο οποίο το λειτουργικό σύστημα βασίζεται σε διακοπές ενώ η διεπαφή χρήστη γίνεται με την ανάπτυξη ενσωματωμένου web server. Με αυτόν τον τρόπο παρέχεται ένα διαδραστικό περιβάλλον που είναι ευρέως διαδεδομένο και με το οποίο ο χρήστης μπορεί να έχει άμεση επαφή με το hardware, ενώ ταυτόχρονα αυτοματοποιεί τη διαδικασία εξαγωγής δεδομένων προσφέροντας αξιοπιστία και υψηλές ταχύτητες. / This thesis presents the development of an embedded system composed of both hardware and software components, for the characterization of a telecommunication prototype. Specifically, we study the control of an advanced telecommunication IP, the automation of collecting interesting data during the operation of the telecommunication device, and ways in available for the engineer to interact with FPGA-based system prototypes. Different techniques of importing and exporting data from the FPGA and storing them to a host system are investigated. The way of importing data and parameters in existing systems presents certain restrictions. In this thesis we study techniques of dynamically importing the data and parameters through a user-friendly environment. We automated the process of collecting data of interest and data retrieval in a secure and reliable manner. To achieve this, an embedded system interface is implemented developing an embedded, on-board web server. The development process includes the use of an embedded processor available as IP block on an FPGA, building a system based on bus channels using virtual addressing, and the connection and the control of telecommunication IP blocks through the bus channel to the processor. The developed system is an embedded system utilizes an interrupt-based operating system offering a user interface based a developed embedded web server. This system provides an interactive environment which is widely used, where the developer can directly access the hardware, and at the same time automates data retrieval and offers reliability and high speed.

This thesis deals with the design of a hardware acceleration unit for digital image filter design using coevolutionary algorithms. The first part introduces reconfigurable logic device technology that the acceleration unit is based on. The theoretical part also briefly characterizes evolutionary and coevolutionary algorithms, their principles and applications. Traditional image filter designs are compared with the biologically inspired design methods. The hardware unit presented in this thesis exploits dual MicroBlaze system extended by custom peripherals to accelerate cartesian genetic programming. The coevolutionary image filter design is accelerated up to 58 times. The hardware platform functionality in the task of impulse noise filter design and edge detector design has been empirically analyzed.

Unmanned Aerial Systems (UAS) are aircraft without a human pilot on board. They are comprised of a ground-based autonomous or human operated control system, an unmanned aerial vehicle (UAV) and a communication, command and control (C3) link between the two systems. UAS are widely used in military warfare, wildfire mapping, aerial photography, etc primarily to collect and process large amounts of data. While they are highly efficient in data collection and processing, they are susceptible to software espionage and data manipulation. This research aims to provide a novel solution to enhance the security of the flight controller thereby contributing to a secure and robust UAS. The proposed solution begins by introducing a new technology in the domain of flight controllers and how it can be leveraged to overcome the limitations of current flight controllers. The idea is to decouple the applications running on the flight controller from the task of data validation. The authenticity of all external data processed by the flight controller can be checked without any additional overheads on the flight controller, allowing it to focus on more important tasks. To achieve this, we introduce an adjacent controller whose sole purpose is to verify the integrity of the sensor data. The controller is designed using minimal resources from the reconfigurable logic of an FPGA. The secondary I/O processor is implemented on an incipient Zynq SoC based flight controller. The soft-core microprocessor running on the configurable logic of the FPGA serves as a first level check on the sensor data coming into the flight controller thereby forming a trusted boundary layer. / Master of Science

Increasingly, soft processors are being considered for use within FPGA-based reliable computing systems. In an environment in which radiation is a concern, such as space, the logic and routing (configuration memory) of soft processors are sensitive to radiation effects, including single event upsets (SEUs). Thus, effective tools are needed to evaluate and estimate how sensitive the configuration memories of soft processors are in high-radiation environments. A high-speed FPGA fault injection system and methodology were created using the Xilinx Radiation Test Consortium's (XRTC's) Virtex-5 radiation test hardware to conduct exhaustive tests of the SEU sensitivity of a design within an FPGA's configuration memory. This tool was used to show that the sensitivity of the configuration memory of a soft processor depends on several variables, including its microarchitecture, its customizations and features, and the software instructions that are executed. The fault injection experiments described in this thesis were performed on five different soft processors, i.e., MicroBlaze, LEON3, Arm Cortex-M0 DesignStart, OpenRISC 1200, and PicoBlaze. Emphasis was placed on characterizing the sensitivity of the MicroBlaze soft processor and the dependence of the sensitivity on various modifications. Seven benchmarks were executed through the various experiments and used to determine the SEU sensitivity of the soft processor's configuration memory to the instructions that were executed. In this thesis, a wide variety of soft processor fault injection results are presented to show the differences in sensitivity between multiple soft processors and the software they run.