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Tang Tze Yeung Eric. / Thesis submitted in: July 2003. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 69-75). / Abstracts in English and Chinese. / ABSTRACT --- p.II / ACKNOWLEDGMENT --- p.II / Chapter 1 --- INTRODUCTION --- p.1 / Chapter 1.1 --- Embedded System --- p.1 / Chapter 1.2 --- Embedded Processor --- p.1 / Chapter 1.3 --- Embedded System Design --- p.3 / Chapter 1.3.1 --- Current Embedded System Design Challenges --- p.3 / Chapter 1.3.2 --- Embedded System Design Trend --- p.4 / Chapter 1.4 --- Efficient Software Development for Microprocessor --- p.8 / Chapter 1.4.1 --- Efficient Software Development Methodology --- p.8 / Chapter 1.5 --- Thesis Organization --- p.10 / Chapter 2 --- SOURCE CODE OPTIMIZATION --- p.11 / Chapter 2.1 --- Source Code Optimization Strategy --- p.11 / Chapter 2.2 --- Source Code Transformations --- p.12 / Chapter 2.2.1 --- Strength Reduction --- p.12 / Chapter 2.2.2 --- Function Inlining --- p.13 / Chapter 2.2.3 --- Table Lookup --- p.13 / Chapter 2.2.4 --- Loop Transformations --- p.13 / Chapter 2.2.5 --- Software Pipelining --- p.15 / Chapter 2.2.6 --- Register Allocation --- p.17 / Chapter 2.3 --- Case Study: Source Code Optimization on the StrongARM (SA1110) Platform --- p.18 / Chapter 2.3.1 --- StrongARM architecture --- p.18 / Chapter 2.3.2 --- StrongARM pipeline hazard illustration --- p.20 / Chapter 2.3.3 --- Source Code Optimization on StrongARM --- p.21 / Chapter 2.3.4 --- Instruction Set Optimization of StrongARM --- p.27 / Chapter 2.4 --- Conclusion --- p.32 / Chapter 3 --- FLOAT-TO-FIXED OPTIMIZATION --- p.33 / Chapter 3.1 --- Introduction to Fixed-point --- p.34 / Chapter 3.1.1 --- Fixed-point representation --- p.34 / Chapter 3.1.2 --- Fixed-point implementation --- p.35 / Chapter 3.1.3 --- Mathematical functions implementation --- p.38 / Chapter 3.2 --- Case Study: Fingerprint Minutiae Extraction Algorithms on the Strong ARM platform --- p.41 / Chapter 3.2.1 --- Fingerprint Verification Overview --- p.42 / Chapter 3.2.2 --- Fixed-point Implementation of Fingerprint Minutiae Extraction Algorithm --- p.49 / Chapter 3.2.3 --- Experimental Results --- p.51 / Chapter 3.3 --- Conclusion --- p.56 / Chapter 4 --- DOMAIN SPECIFIC OPTIMIZATION --- p.57 / Chapter 4.1 --- Case Study: Font Rasterization on the Strong ARM platform --- p.57 / Chapter 4.1.1 --- Outline Font --- p.57 / Chapter 4.1.2 --- Font Rasterization --- p.59 / Chapter 4.1.3 --- Experiments --- p.63 / Chapter 4.2 --- Conclusion --- p.66 / Chapter 5 --- CONCLUSION --- p.67 / BIBLIOGRAPHY --- p.69

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The purpose of this thesis is to explore the design of a multimedia extension Instruction Set Architecture (ISA) for a reconfigurable processor. An Extendable Multimedia Module (EM3) was designed as an optional module for X32V. X32V is a prototype configurable processor simulator developed at Oregon State University by John Mark Matson and Dr. Ben Lee. The EM3 ISA uses Single-Instruction Multiple-Data (SIMD) type instructions to improve the performance of multimedia applications on X32V such as MPEG-4. Two benchmarks based on certain stages of MPEG-4 decompression were developed to test the initial performance enhancements of EM3. The results of these benchmark tests indicate a several fold improvement in clock cycles and the number of instructions executed. This improvement demonstrates the performance increase of X32V and illustrates the effectiveness of SIMD type multimedia extensions. / Graduation date: 2004

A relatively recent development in the late 1980s in processors has been the superscalar processor. Superscalar processors use multiple pipelines in an attempt to achieve higher performance than previous generations of processors. Having multiple pipelines makes it possible to execute more than one instruction per cycle. However, since instructions are not independent of one another, but are interdependent, there is no guarantee that any given sequence of instruction will take advantage of the wider pipeline. One major factor that governs the ability of a processor to discover parallel instructions is the processor's mechanism for decoding and executing instruction. For superscalar processors with the central window design, the number of parallel instructions discovered is dependent on the size of the window. With a large window, the probability that the processor can find more parallel instructions is higher because there are more instruction to choose from. However, the larger the window the longer the critical path and thus lower clock speed. The major theme of this thesis is to find ways to have a large instruction window but still have clock speed comparable to a small instruction window processor. One way to achieve this is to apply the idea of memory interleaving to the processor's instruction window or reservation station design. With interleaving, there are multiple small instruction windows instead of one large window. In the first cycle the first window is used, and the second window is used in the second clock cycle. After all windows are used, the processor returns to the first window. Therefore with the interleaved design only a small portion of the whole instruction window is active at one time. In this way, there can be a large virtual window. Furthermore since the size of individual window is kept small, the clock speed is not affected. The rest of this thesis will explain how this interleaved instruction window scheme works and also list some simulation results to show its performance. / Graduation date: 1997

Thesis (Ph. D.)--University of Texas at Austin, 2002. / Vita. Includes bibliographical references. Available also from UMI Company.

Thesis (Ph. D.)--University of Texas at Austin, 2002. / Vita. Includes bibliographical references (leaves 137-145). Available also in a digital version from Dissertation Abstracts.

Thesis--Ph. D., University of Hong Kong, 1983.