This thesis explores the design and applications of subharmonic mixers in CMOS microwave integrated circuits. First, a 2x down-converting subharmonic mixer is demonstrated with a measured conversion gain of 8 dB using a 2.1 GHz RF signal. Extending the concept of the 2x subharmonic mixer, a 4x subharmonic mixer is proposed that operates in the 12 GHz Ku-band. This circuit is the first 4x subharmonic mixer in CMOS, and achieves a 6 dB conversion gain, which is the highest for any 4x subharmonic mixer regardless of circuit topology or fabrication technology. Furthermore, it achieves very high measured isolation between its ports (e.g. 4LO-RF: 59 dB). Since both the 2x and the 4x subharmonic mixers require a quadrature oscillator, a new oscillator circuit is presented that could be used with either of the aforementioned mixers. This quadrature oscillator uses active superharmonic coupling to establish the quadrature fundamental relationship. The oscillation frequency is 3.0 GHz and the measured output power is -6 dBm. A dual-band mixer/oscillator is also demonstrated that can operate as either a fundamental mixer or a subharmonic mixer depending on a control voltage. This circuit operates from 5.0 GHz to 6.0 GHz or from 9.8 GHz to 11.8 GHz by using either the fundamental output or the second harmonic output of the quadrature oscillator circuit described above and achieves conversion gain over both frequency bands. A novel frequency tripler circuit is presented based on a subharmonic mixer. This circuit uses the 2x subharmonic mixer discussed above, along with a feedforward fundamental cancellation circuit. The measured fundamental suppression is up to 30 dB and the conversion gain is up to 3 dB. Finally, a frequency divider circuit based on a subharmonic mixer is presented that divides the input signal frequency by a factor of three. This circuit uses a single-balanced version of the 2x subharmonic mixer described above in a regenerative divider topology. The measured input signal bandwidth is 300 MHz (5.2 GHz to 5.5 GHz) with an input power of -7 dBm and the maximum conversion gain is 0 dB. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2009-03-24 16:08:31.805

In this thesis, three low-noise active mixing circuits are presented in CMOS technology. Mixers can be found at the front-end of almost every communication systems. However, despite many advantages the active mixers have, one drawback is their poor noise performance. One mixer that has been widely used in integrated circuit is the Gilbert cell. This thesis demonstrated that by merging the low-noise amplifier (LNA) with the Gilbert cell, a low-noise active mixer can be realized. This kind of mixer relaxes the front-end design, allows higher circuit integration, and reduces power consumption. The first circuit is a narrowband low-noise mixer that operates at 5.4 GHz in 0.18 um CMOS. An inductive degenerated LNA is used as the transconductor. Together with a current bleeding circuit, a gain of 13.1 dB and a low 7.8 dB single-sideband noise figure are achieved. The circuit was fabricated and measured. Simulation and measurement results are compared and discussed. The second circuit is a broadband low-noise mixer that operates between 1 and 5.5 GHz in 0.13 um CMOS. The noise-cancelling technique is used to design the transconductors. This technique does not require the use of inductors while able to achieve a sub 3 dB noise figure and input matching over a large bandwidth. To further extend the mixer bandwidth, the series inductive peaking was used. Measured and simulated results showed great agreement. It has a high gain of 17.5 dB, a bandwidth of 4.5 GHz, and a low average double-sideband noise figure of 3.9 dB. This mixer has the best broadband noise performance ever reported in CMOS. Finally, a double-balanced low-noise self-oscillating mixer (SOM) in 0.13 um CMOS is presented. This is a current-reuse, highly integrated circuit that combines an LNA, mixer, and oscillator seamlessly into a single component. The oscillator generates the required LO while serving as the mixer load simultaneously. Measured and simulated results showed excellent agreement. A low double-sideband noise figure of 4.4 dB and a gain of 11.6 dB were measured. This type of SOM and loading structure are the first ever reported. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2009-08-23 12:41:20.445

This thesis explores the design of fast-settling pulse generators and pulsed low noise amplifiers (LNAs) for Ultra-Wideband (UWB) applications. These components are critical in pulsed UWB transceivers, and a high energy efficiency is sought without adversely affecting RF performance and functionality. To this end, new pulse generators with a subnanosecond settling time and a low energy consumption of only a few picojoules per pulse are targeted. Moreover, a novel pulsed LNA is investigated for a low power consumption that can be scaled with the duty cycle. First, an energy-efficient tunable pulse generator is proposed for high-data-rate 3.1-10.6 GHz UWB applications. A current-starved ring oscillator is quickly switched on and off, and the amplitude envelope is shaped using a passive attenuator. The energy consumption per pulse is below 4.2 pJ while the pulse amplitude is 150 mV, yielding a high energy efficiency. A quadrature pulse generator is then presented for 22-29 GHz UWB applications with a settling time below 0.5 ns. An inductor-capacitor (LC) oscillator is quickly switched on and off with a new technique, and the amplitude envelope is shaped using a variable passive attenuator. The energy consumption per pulse is only 6.2 pJ, and the pulse amplitude is more than 240 mV, yielding the highest energy efficiency reported to date in CMOS. Next, a 3-10 GHz pulsed ring oscillator that offers direct quadrature phase modulation is demonstrated. Current impulses are injected into the oscillator to enable fast startup and implement quadrature phase modulation. The energy consumption and voltage swing varies from 13 pJ and 300 mV at 3 GHz to 18 pJ and 200 mV at 10 GHz respectively, yielding a high energy efficiency. Lastly, a fast switching noise cancelling LNA is proposed for 3.1-10.6 GHz UWB applications that settles within 1.3 ns for switching speeds as high as 200 MHz. Inductive peaking is introduced in the noise cancelling topology to achieve a sub-4dB flat noise figure and a high gain of 16.6 dB for frequencies up to 10 GHz. The average power consumption is also below 10 mW with a 50% duty cycle clock. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2011-08-23 15:29:58.93

Layered multiconductor coupled slot and strip-slot structures are characterized by introducing the full-wave modal analysis as well as the quasi-TEM spectral domain technique. In the modal analysis, the electric and magnetic fields are constructed in terms of modal fields in different regions. Application of the boundary conditions at interfaces for the tangential components of the electric and magnetic fields results in the dyadic Green's function, which interrelates the tangential currents and electric fields at the boundaries of the layered structure. The slot fields and strip currents are expanded in terms of a set of known basis functions with unknown coefficients. Use of the Galerkin method leads to a set of algebraic equations. The non-trivial solutions for the propagation constants are found by setting the determinant of the algebraic equations equal to zero. All the other normal mode parameters including the modal impedances, the field and current eigenvectors are then computed by using the solutions of the propagation constants. In the quasi-TEM analysis, the Laplace equation is transformed to an ordinary differential equation in the spectral domain, the solution of which together with the boundary conditions yields the Green's function which interrelates the potential and the charge distribution at the interfaces of the layered structure. The charge distribution is expanded in terms of known functions with unknown coefficients which are subsequently evaluated by applying the Galerkin method. Once the charge distribution is found, the quasi-TEM characteristics of the coupled strip-slot structures are readily calculated. Different impedance definitions proposed in the literature for multiple coupled line structures are discussed. The only useful impedance definition in the design of microwave and millimeter-wave circuits is the one that results in a symmetric impedance matrix for a coupled line structure in a lossless, isotropic, and linear medium. The normal mode impedance definition as based on the reciprocity is used to systematically study the impedance characteristics of various coupled slot structures for the first time, which together with the propagation characteristics are used to compute equivalent circuit models for ideal coupled line structures. The applications of the coupled slot and strip-slot structures are illustrated through design examples of enhanced couplers and power dividers consisting of coupled line multiports. Time domain simulation of coupled multiconductor structures with slotted ground planes is also presented to exemplify the applications of the techniques developed in this thesis to layered interconnects and packaging structures in high-speed circuits. Some novel techniques to reduce the crosstalk noise in those structures are proposed with theoretical examples and experimental results. / Graduation date: 1994

Thesis (Ph.D.) - Carleton University, 2005. / Includes bibliographical references (p. 170-180). Also available in electronic format on the Internet.

No description available.

Thesis (M. App. Sc.)--Carleton University, 2004. / Includes bibliographical references (p. 110-113). Also available in electronic format on the Internet.

Recent years have shown real advances of microwave monolithic integrated circuits (MMICs) for millimeter-wave frequency systems, such as wireless communication, advanced imaging, remote sensing and automotive radar systems, as MMICs can provide the size, weight and performance required for these systems. Traditionally, GaAs pseudomorphic high electron mobility transistor (pHEMT) or InP based MMIC technology has dominated in millimeter-wave frequency applications because of their high fT and fmax as well as their superior noise performance. But these technologies are very expensive. Thus, for low cost and high performance applications, InGaP/GaAs heterojunction bipolar transistors (HBTs) are quickly becoming the preferred technology to be used due to their inherently excellent characteristics. These features, together with the need for only one power supply to bias the device, make InGaP/GaAs HBTs very attractive for the design of high performance fully integrated MMICs. With the smaller dimensions for improving speed and functionality of InGaP/GaAs HBTs, which dissipate large amount of power and result in heat flux accumulated in the device junction, technology reliability issues are the first concern for the commercialization. As the thermally triggered instabilities often seen in InGaP/GaAs HBTs, a carefully derived technique to define the stress conditions of accelerated life test has been employed in our study to acquire post-stress device characteristics for the projection of long-term device performance degradation pattern. To identify the possible origins of the post-stress device behaviors observed experimentally, a two iv dimensional (2-D) TCAD numerical device simulation has been carried out. Using this approach, it is suggested that the acceptor-type trapping states located in the emitter bulk are responsible for the commonly seen post-stress base current instability over the moderate base-emitter voltage region. HBT-based MMIC performance is very sensitive to the variation of core device characteristics and the reliability issues put the limit on its radio frequency (RF) behaviors. While many researchers have reported the observed stress-induced degradations of GaAs HBT characteristics, there has been little published data on the full understanding of stress impact on the GaAs HBTbased MMICs. If care is not taken to understand this issue, stress-induced degradation paths can lead to built-in circuit failure during regular operations. However, detection of this failure may be difficult due to the circuit complexity and lead to erroneous data or output conditions. Thus, a practical and analytical methodology has been developed to predict the stress impacts on HBTbased MMICs. It provides a quick way and guidance for the RF design engineer to evaluate the circuit performance with reliability considerations. Using the present existing EDA tools (Cadance SpectreRF and Agilent ADS) with the extracted pre- and post-stress transistor models, the electrothermal stress effects on InGaP/GaAs HBT-based RF building blocks including power amplifier (PA), low-noise amplifier (LNA) and oscillator have been systematically evaluated. This provides a potential way for the RF/microwave industry to save tens of millions of dollars annually in testing costs. v The world now stands at the threshold of the age of advanced GaAs HBT MMIC technology and researchers have been exploring here for years. The reliability of GaAs HBT technology is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation provide methods and guidance for the RF designers to achieve more reliable RF circuits with advanced GaAs HBT technology in the future.

<p>This thesis considers integration of antennas and active electronics manufactured on the same substrate. The main topic is on-chip antennas for commercial silicon processes, but hybrid integration using printed circuit board technology is also addressed.</p><p>The possible use of micromachining techniques as a means of reducing substrate losses of antennas manufactured on low resistivity silicon wafers is investigated. Compact dipole, loop, and inverted-F antennas for the 20-40 GHz frequency range are designed, implemented, and characterized. The results show significantly improved antenna efficiency when micromachining is used as a post-processing step for on-chip antennas manufactured in silicon technology.</p><p>High resistivity wafers are used in a commercial silicon germanium technology to improve the efficiency of dipole antennas realized using the available circuit metal layers in the process. Monolithically integrated 24 GHz receivers with on-chip antennas are designed and evaluated with regard to antenna and system performance. No noticeable degradation of the receiver performance caused by cross talk between the antenna and the integrated circuit is observed.</p><p>For low frequency antenna arrays, such as base station antennas, hybrid integration of active devices within the antenna aperture is treated. A compact varactor based phase shifter for traveling wave antenna applications is proposed and evaluated. Electrically steerable traveling wave patch antenna arrays, with the phase shifters implemented in the same conductor layer as the radiating elements, are designed and manufactured in microstrip technology. It is experimentally verified that the radiation from the feed network and phase shifters in the proposed antenna configuration is small.</p>

This thesis considers integration of antennas and active electronics manufactured on the same substrate. The main topic is on-chip antennas for commercial silicon processes, but hybrid integration using printed circuit board technology is also addressed. The possible use of micromachining techniques as a means of reducing substrate losses of antennas manufactured on low resistivity silicon wafers is investigated. Compact dipole, loop, and inverted-F antennas for the 20-40 GHz frequency range are designed, implemented, and characterized. The results show significantly improved antenna efficiency when micromachining is used as a post-processing step for on-chip antennas manufactured in silicon technology. High resistivity wafers are used in a commercial silicon germanium technology to improve the efficiency of dipole antennas realized using the available circuit metal layers in the process. Monolithically integrated 24 GHz receivers with on-chip antennas are designed and evaluated with regard to antenna and system performance. No noticeable degradation of the receiver performance caused by cross talk between the antenna and the integrated circuit is observed. For low frequency antenna arrays, such as base station antennas, hybrid integration of active devices within the antenna aperture is treated. A compact varactor based phase shifter for traveling wave antenna applications is proposed and evaluated. Electrically steerable traveling wave patch antenna arrays, with the phase shifters implemented in the same conductor layer as the radiating elements, are designed and manufactured in microstrip technology. It is experimentally verified that the radiation from the feed network and phase shifters in the proposed antenna configuration is small.