Channel coding plays a vital role in telecommunication. Low-Density Parity- Check (LDPC) codes are linear error-correcting codes. According to the 3rd Generation Partnership Project (3GPP) TS 38.212, LDPC is recommended for the Fifth-generation (5G) New Radio (NR) shared channels due to its high throughput, low latency, low decoding complexity and rate compatibility. LDPC encoding chain has been defined in 3GPP TS 38.212, but some details of LDPC encoding chain are still required to be explored in the MATLAB environment. For example, how to deal with the filler bits for encoding and decoding. However, as the reverse process of LDPC encoding, there is no information on LDPC decoding process for 5G NR shared channels in 3GPP TS 38.212. In this thesis project, LDPC encoding and decoding chains were thoughtfully developed with MATLAB programming based on 3GPP TS 38.212. Several LDPC decoding algorithms were implemented and optimized. The performance of LDPC algorithms was evaluated using block error rate (BLER) v.s. signal to noise ratio (SNR) and CPU time. Results show that the double diagonal structure-based encoding method is an efficient LDPC encoding algorithm for 5G NR. Layered Sum Product Algorithm (LSPA) and Layered Min-Sum Algorithm (LMSA) are more efficient than Sum Product Algorithm (SPA) and Min-Sum Algorithm (MSA). Layered Normalized Min-Sum Algorithm (LNMSA) with proper normalization factor and Layered Offset Min-Sum Algorithm (LOMSA) with good offset factor can optimize LMSA. The performance of LNMSA and LOMSA decoding depends more on code rate than transport block. / Kanalkodning spelar en viktig roll i telekommunikation. Paritetskontrollkoder med låg densitet (LDPC) är linjära felkorrigeringskoder. Enligt tredje generationens partnerskapsprojekt (3GPP) TS 38.212, LDPC rekommenderas för den femte generationens (5G) nya radio (NR) delade kanal på grund av dess höga genomströmning, låga latens, låga avkodningskomplexitet och hastighetskompatibilitet. LDPC kodningskedjan har definierats i 3GPP TS 38.212, men vissa detaljer i LDPC kodningskedjan krävs fortfarande för att utforskas i Matlabmiljön. Till exempel hur man hanterar fyllnadsbitar för kodning och avkodning. Men som den omvända processen för LDPC kodning finns det ingen information om LDPC avkodningsprocessen för 5G NR delade kanaler på 3GPP TS 38.212. I detta avhandlingsprojekt utvecklades LDPC-kodning och avkodningskedjor enligt 3GPP TS 38.212. Flera LDPC-avkodningsalgoritmer implementerades och optimerades. Prestandan för LDPC-algoritmer utvärderades med användning av blockfelshalt (BLER) v.s. signal / brusförhållande (SNR) och CPU-tid. Resultaten visar att den dubbla diagonala strukturbaserade kodningsmetoden är en effektiv LDPC kodningsalgoritm för 5G NR. Layered Sum Product Algorithm (LSPA) och Layered Min-Sum Algorithm (LMSA) är effektivare än Sum Product Algorithm (SPA) och Min-Sum Algorithm (MSA). Layered Normalized Min-Sum Algorithm (LNMSA) med rätt normaliseringsfaktor och Layered Offset Min-Sum Algorithm (LOMSA) med bra offsetfaktor kan optimera LMSA. Prestandan för LNMSA- och LOMSA-avkodning beror mer på kodhastighet än transportblock.

A Factor Graph (FG -- http://en.wikipedia.org/wiki/Factor_graph) is a structure used to find solutions to problems that can be represented as a Probabilistic Graphical Model (PGM). They consist of interconnected variable nodes and factor nodes, which iteratively compute and pass messages to each other. FGs can be applied to solve decoding of forward error correcting codes, Markov chains and Markov Random Fields, Kalman Filtering, Fourier Transforms, and even some games such as Sudoku. In this paper, a framework is presented for rapid prototyping of hardware implementations of FG-based applications. The FG developer specifies aspects of the application, such as graphical structure, factor computation, and message passing algorithm, and the framework returns a design. A system of Python scripts and Verilog Hardware Description Language templates together are used to generate the HDL source code for the application. The generated designs are vendor/platform agnostic, but currently target the Xilinx Virtex-6-based ML605. The framework has so far been primarily applied to construct Low Density Parity Check (LDPC) decoders. The characteristics of a large basket of generated LDPC decoders, including contemporary 802.11n decoders, have been examined as a verification of the system and as a demonstration of its capabilities. As a further demonstration, the framework has been applied to construct a Sudoku solver. / Master of Science

Σε αυτή την εργασία μελετάμε τους αλγορίθμους που χρησιμοποιούνται στην αποκωδικοποίηση των LDPC, με έμφαση στους κώδικες του προτύπου 802.11n. Αντιμετωπίζουμε τις δυσκολίες που αντιμετωπίζουν στην υλοποίηση στο υλικό, κυρίως στην εκτέλεση αριθμητικών πράξεων, και προτείνουμε πρακτικές λύσεις. Χρησιμοποιώντας τα αποτελέσματα εκτενών εξομοιώσεων, καταλήγουμε στις βέλτιστες παραμέτρους που θα έχουν οι προτεινόμενες υλοποιήσεις. / In this thesis, we study the LDPC decoding algorithms, with emphasis on the 802.11n standard codes. We tackle the hardware implementation difficulties, especially those related to arithmetic computations, and propose practical solutions. Leveraging the results of extensive simulations, we find the optimal parameters of the proposed implementations.

This dissertation studies methods to achieve reliable communication over unreliable channels. Iterative decoding algorithms for low-density parity-check (LDPC) codes and generalized LDPC (GLDPC) codes are analyzed. A new class of error-correcting codes to enhance the reliability of the communication for high-speed systems, such as optical communication systems, is proposed. The class of spatially-coupled GLDPC codes is studied, and a new iterative hard- decision decoding (HDD) algorithm for GLDPC codes is introduced. The main result is that the minimal redundancy allowed by Shannon’s Channel Coding Theorem can be achieved by using the new iterative HDD algorithm with spatially-coupled GLDPC codes. A variety of low-density parity-check (LDPC) ensembles have now been observed to approach capacity with iterative decoding. However, all of them use soft (i.e., non-binary) messages and a posteriori probability (APP) decoding of their component codes. To the best of our knowledge, this is the first system that can approach the channel capacity using iterative HDD. The optimality of a codeword returned by the weighted min-sum (WMS) algorithm, an iterative decoding algorithm which is widely used in practice, is studied as well. The attenuated max-product (AttMP) decoding and weighted min-sum (WMS) decoding for LDPC codes are analyzed. Applying the max-product (and belief- propagation) algorithms to loopy graphs are now quite popular for best assignment problems. This is largely due to their low computational complexity and impressive performance in practice. Still, there is no general understanding of the conditions required for convergence and/or the optimality of converged solutions. This work presents an analysis of both AttMP decoding and WMS decoding for LDPC codes which guarantees convergence to a fixed point when a weight factor, β, is sufficiently small. It also shows that, if the fixed point satisfies some consistency conditions, then it must be both a linear-programming (LP) and maximum-likelihood (ML) decoding solution.

The VLSI implementation complexity of a low density parity check (LDPC) decoder is largely influenced by the interconnect and the storage requirements. This dissertation presents the decoder architectures for regular and irregular LDPC codes that provide substantial gains over existing academic and commercial implementations. Several structured properties of LDPC codes and decoding algorithms are observed and are used to construct hardware implementation with reduced processing complexity. The proposed architectures utilize an on-the-fly computation paradigm which permits scheduling of the computations in a way that the memory requirements and re-computations are reduced. Using this paradigm, the run-time configurable and multi-rate VLSI architectures for the rate compatible array LDPC codes and irregular block LDPC codes are designed. Rate compatible array codes are considered for DSL applications. Irregular block LDPC codes are proposed for IEEE 802.16e, IEEE 802.11n, and IEEE 802.20. When compared with a recent implementation of an 802.11n LDPC decoder, the proposed decoder reduces the logic complexity by 6.45x and memory complexity by 2x for a given data throughput. When compared to the latest reported multi-rate decoders, this decoder design has an area efficiency of around 5.5x and energy efficiency of 2.6x for a given data throughput. The numbers are normalized for a 180nm CMOS process. Properly designed array codes have low error floors and meet the requirements of magnetic channel and other applications which need several Gbps of data throughput. A high throughput and fixed code architecture for array LDPC codes has been designed. No modification to the code is performed as this can result in high error floors. This parallel decoder architecture has no routing congestion and is scalable for longer block lengths. When compared to the latest fixed code parallel decoders in the literature, this design has an area efficiency of around 36x and an energy efficiency of 3x for a given data throughput. Again, the numbers are normalized for a 180nm CMOS process. In summary, the design and analysis details of the proposed architectures are described in this dissertation. The results from the extensive simulation and VHDL verification on FPGA and ASIC design platforms are also presented.

Low-Density Parity-Check (LDPC) codes are linear error-correcting codes used to establish reliable communication between units on a noisy transmission channel in mobile telecommunications. LDPC algorithms detect and recover altered or corrupted message bits using sparse parity-check matrices in order to decipher messages correctly. LDPC codes have been shown to be fitting coding schemes for the fifth generation (5G) New Radio (NR), according to the third generation partnership project (3GPP).  TietoEvry, a consultant in telecom, has discovered that optimizations of LDPC decoding algorithms can be achieved/obtained with the use of a parallel computing platform called Compute Unified Device Architecture (CUDA), developed by NVIDIA. This platform utilizes the capabilities of a graphics processing unit (GPU) rather than a central processing unit (CPU), which in turn provides parallel computing. An optimized version of an LDPC decoding algorithm, the Min-Sum Algorithm (MSA), is implemented in CUDA and in C++ for comparison in terms of CPU execution time, to explore the capabilities that CUDA offers. The testing is done with a set of 12 sparse parity-check matrices and input-channel messages with different sizes. As a result, the CUDA implementation executes approximately 55% faster than a standard, unoptimized C++ implementation.