No description available.

No description available.

The growing demand for high performance systems in modern computing technology drives the development of advanced and high speed designs in I/O structures. Due to their data rate and architecture, however, testing of the high speed serial interfaces becomes more expensive when using conventional test methods. In order to alleviate the test cost issue, a loopback test scheme has been widely adopted. To assess the margin of the signal eye in the loopback configuration, the eye margin is purposely reduced by additional devices on the loopback path or using design for testability (DFT) features such as timing and voltage margining. Although the loopback test scheme successfully reduces the test cost by decoupling the dependency of external test equipment, it has robustness issues such as a fault masking issue and a non-ideality problem of margining circuits. The focus of this dissertation is to propose new methods to resolve the known issues in the loopback test mode. The fault masking issue in a loopback pair of analog to digital and digital to analog converters (ADC and DAC) which can be found in pulse amplitude modulation (PAM) signaling schemes is resolved using a proposed algorithm which separates the characteristics of the ADC and the DAC from a combined loopback response. The non-ideality problem of margining circuit is resolved using a proposed method which utilizes a random jitter injection technique. Using the injected random jitter, the jitter distribution is sampled by undersampling and margining, which provides the nonlinearity information using the proposed algorithm. Since the proposed method requires a random jitter source on the load board, an alternative solution is proposed which uses an intrinsic jitter profile and a sliding window search algorithm to characterize the nonlinearities. The sliding search algorithm was implemented in a low cost high volume manufacturing (HVM) tester to assess feasibility and validity of the proposed technique. The proposed methods are compatible with the existing loopback test scheme and require a minimal area and design overhead, hence they provide cost effective ways to enhance the robustness of the loopback test scheme. / text

No description available.

No description available.

Conventionally, the performances of Analog and Mixed-Signal (AMS) circuits have been characterized using specification-based functional tests. In these test methods, the correct functionalities of AMS circuits are verified by measuring pre-determined specification parameters of AMS circuits. The conventional test methods provide accurate test results by using various test equipments which generate functional test signals and capture the test responses externally. However, due to rapid increase in the performance of AMS circuits in recent years, the conventional test methods face various challenges in the aspects of test cost, test time and testability. The goal of this dissertation is to develop innovative functional test methods for AMS circuits which are aimed at reducing the test cost and test time while providing comparable test accuracy to the conventional test methods. To achieve this goal, efforts have been made to explore the characteristics of AMS circuits in a system level and to research efficient performance characterization methods based on the system level modeling of Devices Under Test (DUTs). As a part of these efforts, the pseudorandom test methods for nonlinear AMS circuits have been developed. In these methods, the pseudorandom signal is used to excite the DUT and to generate the test response which has sufficient information to characterize DUT performances. The pseudorandom test methods use the Volterra series model to capture the nonlinear behaviors of AMS circuits and to calculate various specification parameters of the DUT using the pseudorandom test response. In doing so, the performances of nonlinear AMS circuits can be characterized straightforwardly and accurately using a low-cost test setup. Also, in an effort to reduce the test time, parallel test methods of AMS circuits have been developed in which multiple DUTs are tested simultaneously by sharing a common test setup. In these methods, the test responses generated from different DUTs are combined together and the resulting composite test response is used to characterize the performance of each DUT individually. This will reduce the use of tester resources and will increase the test throughput beyond the level limited by the test equipments. The spectral characteristics of test stimulus are studied along with the system level behavior of AMS circuits to develop the efficient parallel test methods. Finally, in order to consider the practical issue of generating at-speed test stimuli for high-speed DUTs using a low-cost test setup, a reconfigurable built-off test interface is developed which can be used to generate various test patterns, including high-speed pseudorandom signal, using a low-speed tester. / text

L'acoblament de soroll a través del substrat en circuits integrats mixtos és un important problema que sovint limita les prestacions de la circuiteria analògica. Les característiques d'aquest tipus d'acoblament i els factors que en determinen la importància no són ben compresos, així que calen criteris per tal de triar les millor accions per a resoldre el problema. En els darrers anys s'han proposat algunes tècniques per reduir el soroll de substrat, tot i que no hi ha una idea clara de l'abast de la seva validesa, i de les condicions que calen per a la seva eficàcia. La majoria de l'esforç de recerca que s'ha dedicat a aquest tema s'ha centrat en el desenvolupament de models, que permetin la incorporació del substrat en les eines CAD que s'utilitzen en les fases de simulació dels dissenys. Per tant, aquests resultats de recerca no contribueixen a la comprensió dels aspectes rellevants de l'acoblament.En aquesta tesi doctoral s'ha realitzat un estudi analític i experimental que ha permès determinar les característiques tecnolòiques i de disseny que faciliten l'acoblament vers la circuiteria analògica. S'ha partit d'una caracterització de l'acoblament mitjançant un simulador de dispositius, on s'ha pogut comprovar la importància d'aspectes com el tipus de substrat, la velocitat de commutació dels dispositius, les seves dimensions, o el punt de polarització. La caracterització s'ha realitzat tant per tecnologies CMOS com BiCMOS, i ha estat completada amb mesures sobre estructures de test. Posteriorment s'ha portat a terme un anàlisi de la propagació del soroll en el substrat, amb el que s'han esbrinat les característiques tecnològiques i de polartizació que determinen l'atenuació del soroll. L'anàlisis'ha realizat suposant condicions de polarització ideals, i ha permès determinar el potencial d'algunes mesures per a la minimització de l'acoblament. A continuació s'ha fet una revisió de les diverses tècniques de modelació del substrat, i utilitzant algun dels models s'han pogut realitzar simulacions circuitals per a estudiar l'acoblament en circuits de dimensions realistes, tenint en compte factors com els elements paràsits dels terminals de l'encapsulat, la influència dels pads, o l'estratègia de polarització. Aquest estudi s'ha complementat amb el disseny d'un circuit mixte de test sobre el que s'han fet mesures per a verificar els resultats obtinguts, i corroborar els mecanismes que determinen l'acoblament. La tesi s'ha completat amb una revisió de l'eficàcia d'algunes tècniques específiques per a la reducció del soroll, i amb un estudi de l'evolució en tecnologies futures tant del soroll de commutació a les línies d'alimentació, com del soroll acoblat a través del substrat. / El acoplo de perturbaciones a través del sustrato de silicio en circuitos integrados mixtos representa un importante problema que a menudo limita las prestaciones de la circuiteria analógica. Hay una cierta incomprensión de las características del acoplo i de los factotres que que determinan su importancia, de forma que faltan criterios para implementar técnicas que reduzcan el problema. En los últimos años se han propuesto diversas técnicas para la reducción del ruido de sustrato, aunque no estan claros su rango de validez y las condiciones que se deben cumplir para su eficacia. La mayor parte del esfuerzo investigador realizado en este campo se ha centrado en el desarrollo de modelos que faciliten la incorporación del sustrato a las herramientas CAD utilizadas en la fase de simulación de un circuito. Por tanto, esta investigación no ofrece aportaciones en la comprensión de los aspectos relevantes del fenómeno.En esta tesis doctoral se ha realilzado un estudio analítico y experimental que ha permitido determinar las características tecnológicas y de diseño que facilitan el acoplo sobre la circuitería analógica. Se ha partido de una caracterización del acoplamiento mediante un simulador de dispositivos, donde se ha podido comprovar la importancia de aspectos como el tipo de sustrato, la velocidad de conmutación de los dispositivos, sus dimensiones, o el punto de polarización. La caracterización se ha realizado tanto para estructuras CMOS como BiCMOS, y ha sido completada con medidas sobre estructuras de test. Posteriomente se ha llevado a cabo un análisis de la propagación del ruido en el sustrato, con el que se han determinado las características tecnológicas y de polarización que determinan la atenuación del ruido. El análisis se ha realizado suponiendo condiciones de polarización ideales, y ha permitido determinar el potencial de algunas medidas para la minimización del acoplo. A continuación se ha realizado una revisión de las diversas técnicas de modelación del sustrato, y utilizando alguno de los modelos se han podido realizar simulaciones circuitales para estudiar el acoplo en circuitos de dimensiones realistas, teniendo en cuenta factores como los elementos parásitos de los terminales del encapsulado, la influencia de los pads, o la estrategia de polarización. Este estudio se ha complementado con el diseño de un circuito mixto de test sobre el que se han hecho medidas para verificar los resultados obtenidos, y corroborar los mecanismos que determinan el acoplo. La tesi se ha completado con una revisión de la eficacia de algunas técnicas específicas para la reducción del ruido, y con un estudio de la evolución en tecnologías futuras tanto del ruido de conmutación a través de las líneas de alimentación, como del ruido acoplado a través del sustrato. / Noise coupling through common silicon substrate in mixed-signal circuits is an important problem that often limits the performance of the analog circuitry. The characteristics of this type of coupling and the factors determining its importance are not well understood, so criteria to choose the best actions to solve the problem are needed. Several techniques to reduce substrate noise have been proposed in the last years, although there is no clear idea about their range of validity, and the conditions required for their efficacy. Most of the research effort done in this field has been centered on the development of models, in order to allow the incorporation of substrate in the CAD tools used in simulation design stages. Thus, these research results do not contribute to the understanding of the relevant aspects of coupling.In this thesis an analytic and experimental study has been done, which has allowed determining the technological and design characteristics relevant in the coupling. The study has started with a characterisation of coupling using a device simulator, which has allowed determining the importance of aspects such as substrate type, device switching speed, device dimensions, or their biasing. Characterisation has been done both for CMOS and BiCMOS technologies, and it has been completed with measurements on test structures. Next an analysis of noise propagation through the substrate has been carried out, which has allowed to find out the biasing and technological characteristics that determine noise attenuation. The analysis has been done assuming ideal biasing conditions, and the potentiality of some noise minimisation measures could be determined. Next a review of the different substrate modelling techniques has been done, and some of the models have been used to perform circuit simulations to study coupling in circuits of some complexity, taking into account factors such as package pins parasitics, the influence of the ring of pads, or the biasing strategy. This study has been complemented with the design and measurements of a mixed-signal test circuit, which allowed verification of the results previously obtained, and the coupling mechanism. Finally the thesis is completed with a review of the efficacy of noise-reducing specific techniques, and with the study of the trends of switching noise on power supply lines and substrate for near future technologies.

A dual-mode second-order Multirate Multibit Sigma Delta (MM-SD) modulator is implemented in a 90nm digital CMOS process for application in the baseband path of RF receivers. Low power consumption is achieved through a new integrator structure and a dedicated timing scheme along with aggressive capacitor scaling in the second stage of the modulator loop. Fabricated prototype achieves 68.6dB peak Signal-to-Noise and Distortion ratio (SNDR) in the 200 kHz GSM band and requires 1.1mA of total current from a 1.5V supply. This dual-mode design also achieves 42.8dB SNDR in the 1.94 MHz WCDMA band with only 1.9mA of total current consumption.

With the evolution of technologies, mixed-signal system integration is becoming necessary for combining heterogeneous functions such as high-speed processors, radio frequency (RF) circuits, memory, microelectromechanical systems (MEMS), sensors, and optoelectronic devices. This kind of integration is required for convergent microsystems that support communication and computing capabilities in a tightly integrated module. A major bottleneck with such heterogeneous integration is the noise coupling between the dissimilar blocks constituting the system. The noise generated by the high-speed digital circuits can couple through the power distribution network (PDN) and this noise can transfer to sensitive RF circuits, completely destroying the functionality of noise-sensitive RF circuits. One common method used for mixed-signal integration in the package is splitting the power and/or ground planes. The gap in the power and ground planes can partially block the propagation of electromagnetic waves. However, electromagnetic energy can still couple through the split, especially at frequencies greater than 1 GHz. The AI-EBG structure in this dissertation has been developed to suppress unwanted noise coupling in mixed-signal systems and this AI- EBG structure shows excellent isolation (-80 dB ~ -140 dB), which results in a noise coupling-free environment in mixed-signal systems. The AI-EBG structure would be part of the power distribution network (PDN) in systems and is expected to have a significant impact on noise suppression and isolation in mixed-signal systems in future.

As CMOS technologies move to sub-100nm regions, the design and verification for analog/mixed-signal circuits become more and more difficult due to the problems including the decrease of transconductance, severe gate leakage and profound mismatches. The increasing manufacturing-induced process variations and their impacts on circuit performances make the already complex circuit design even more sophisticated in the deeply scaled CMOS technologies. Given these barriers, efforts are needed to ensure the circuits are robust and optimized with consideration of parametric variations. This research presents innovative computer-aided design approaches to address three such problems: (1) large analog/mixed-signal performance modeling under process variations, (2) yield-aware optimization for complex analog/mixedsignal systems and (3) on-chip test scheme development to detect and compensate parametric failures. The first problem focus on the efficient circuit performance evaluation with consideration of process variations which serves as the baseline for robust analog circuit design. We propose statistical performance modeling methods for two popular types of complex analog/mixed-signal circuits including Sigma-Delta ADCs and charge-pump PLLs. A more general performance modeling is achieved by employing a geostatistics motivated performance model (Kriging model), which is accurate and efficient for capturing stand-alone analog circuit block performances. Based on the generated block-level performance models, we can solve the more challenging problem of yield-aware system optimization for large analog/mixed-signal systems. Multi-yield pareto fronts are utilized in the hierarchical optimization framework so that the statistical optimal solutions can be achieved efficiently for the systems. We further look into on-chip design-for-test (DFT) circuits in analog systems and solve the problems of linearity test in ADCs and DFT scheme optimization in charge-pump PLLs. Finally a design example of digital intensive PLL is presented to illustrate the practical applications of the modeling, optimization and testing approaches for large analog/mixed-signal systems.