Mixed-signal designs are becoming more and more complex every day. In order to adapt to the new market requirements, a formal process for design and verification of mixed signal systems i. e. top-down design and bottom-up verification methodology is required. This methodology has already been established for digital design. The goal of this research is to propose a new design methodology for mixed signal systems. In the first two chapters of this thesis, the need for a mixed signal design flow based on top-down design methodology will be discussed. The proposed design flow is based on behavioral modeling of the mixed signal system using one of the mixed signal behavioral modeling languages. These models can be used for design and verification through different steps of the design from system level modeling to final physical design. The other advantage of the proposed flow is analog and digital co-design. In the remaining chapters of this thesis, the proposed design flow was verified by designing an 800 MHz mixed signal PLL. The PLL uses a charge pump phase frequency detector, a single capacitor loop filter, and a feed forward error correction architecture using an active damping control circuit instead of passive resistor in loop filter. The design was done in 0. 18- <i>??</i> m CMOS process technology.

Este trabalho propõe o desenvolvimento de uma metodologia para a verificação circuitos integrados de sinais mistos de uso em sistemas de comunicação que operem em modo simplex. Deseja-se aproveitar as características inversas de recepção e transmissão para otimizar o processo de verificação. Para o desenvolvimento desta metodologia de verificação, teve-se como objetivo estudar metodologias de verificação de circuitos integrados de sinais mistos existentes e sua evolução, as quais têm garantido cada vez mais a funcionalidade de circuitos integrados que são compostos por blocos analógicos e digitais. A metodologia é aplicada a um dos circuitos que compõem um sistema otimizado de transmissão de dados via satélite (Transponder para Satélite). O sistema de transmissão de dados via satélite, foco do trabalho, é composto por receptores, transmissores e conversores analógico digital e um Processador Digital de Sinais - Digital Signal Processing (DSP), todos desenvolvidos em hardware. A metodologia de verificação compreende no desenvolvimento de uma estrutura de verificação capaz de estimular os blocos digitais e analógicos com o objetivo de garantir a funcionalidade de cada um dos componentes do IP Transponder. Em uma etapa seguinte, foi possível estimular o IP Transponder de forma integrada, no que se refere aos os blocos digitais e analógicos, assim como os de transmissão e recepção. Ressalta-se ainda que todo o desenvolvimento foi realizado em alto nível, ou seja, todas as características e propriedades foram observadas utilizando-se somente simuladores para garantir a funcionalidade do circuito integrado de sinais mistos que compõe o IP Transponder para satélite. / This work proposes the development of a verification methodology, used during the verification process of a mixed signal integrated circuit, which represents a communication system operating in simplex mode. In order to optimize the verification process, reverse reception and transmission will be used. With the intention of developing our verification methodology, a study on other methodologies used for the verification of mixed signals integrated circuits and the evolution of such methodologies was carried out. The proposed methodology has been applied in an advanced circuit used to establish data transmission by satellite (Transponder for Satellite). The targeted data transmission system is composed by analog receptor and transmitter, analog to digital converters and a digital signal-processing unit, all developed in hardware. The verification methodology consists of two steps: first, the development of a verification structure that are able to stimulate digital and analog blocks in order to guarantee the functionality of each system component. In a following step, the developed verification environment provides the stimulation for all the Transponder IP (digital and analog blocks), and for transmission and reception blocks as well. The verification process development was performed in high level, meaning all the characteristics and properties has been observed using only simulators with the purpose of guarantee the functionality of the mixed signal integrated circuit that composes the satellite Transponder IP.

To solve these issues, in this thesis the consistent effort in developing a quick tools assisted IC design platform is presented. First, a reconfigurable solution is proposed for some analog/mixed-signal (AMS) system which requires flexibility to a certain extent, such as a reconfigurable RFID solution for different communicating distances. Second, for further demand of increasing the flexibility, a novel approach for ADA is presented, which provides a highly automatic design flow for analog circuits to realize the "SPEC (Specification) in, GDS out" goal. Considering all kinds of higher order effects and uncertainties under deep submicron or even more advanced technologies, reliable design and fastness in processing are the two major concerns instead of the traditional pure optimization for best performance. To get a good balance among performance, reliability and turnaround time, an Application-Specific design flow with in-built knowledge-based algorithms is applied to deal with ADA issues under advanced technologies, which can quickly provide a reliable design with performance good enough to meet the SPECs for common use. / Unlike the highly automatic flow for digital circuits design, analog design automation (ADA) is still far from mature. For mixed-signal applications, analog circuit occupies only a small part on the layout, but the design requires a considerable amount of time and effort, making ADA extremely attractive. However, there are a lot more considerations to cover in analog design flow than its digital counterparts. In addition, the ever downscaling IC means analog circuits have to face more and more small-size effects, insufficient modelings, and the inaccuracy of classic formulas, which are quite difficult to handle. To solve the problem, various tools and methods have been proposed, but all in a digital-like flow, which are trying to develop general algorithms to realize circuit and layout synthesis. Up to now there is still a lot of problems. / Hong, Yang. / Adviser: C.S. Choy. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 140-150). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Le développement croissant de systèmes embarqués de consommation, où les composants numériques, analogiques et logiciels sont combinés sur une même puce, résulte en une augmentation de la complexité des processus de conception et de vérification. La validation de tels systèmes analogiques et à signaux-mixtes reste largement basée sur des techniques de simulation, qui sont souvent combinées avec des méthodes d'analyse de nature ad-hoc. Cette thèse est motivée par l'exportation de méthodes formelles basées sur des propriétés, vers leur application à la validation de systèmes analogiques et à signaux mixtes, considérés à leur niveaux d'abstraction continu et temporisé.<br />Etant-donné que la vérification formelle de systèmes continus non-triviaux reste très difficile, nous nous tournons vers une méthode de validation plus légère appelée le monitoring basé sur des propriétés. Nous définissons signal temporal logic STL comme langage de spécification de haut niveau qui permet d'exprimer des propriétés temporelles de signaux continus et temporisés. STL est une extension de la logique de temps-réel metric interval temporal logic MITL, où les signaux continus sont transformés en signaux Booléens avec des prédicats numériques, et les relations temporelles entre ces signaux son exprimées avec les opérateurs temporels habituels dont les propositions atomiques correspondent à ces prédicats. Nous développons deux procédures de monitoring, une offline et une incrémantale, qui permettent de vérifier si les traces de simulations sont correctes par rapport aux propriétés STL. Les deux procédures sont implantées en outil de monitoring analogique AMT. Notre approche de monitoring basé sur des propriétés est appliquée, en utilisant AMT, à deux études de cas réalistes, où nous étudions des propriétés d'une mémoire de type FLASH et d'une interface de mémoire DDR2. <br />Nous considérons aussi le problème de vérification formelle de systèmes temporisés, et développons une traduction modulaire des formules MITL avec les opérateurs futurs et passés, vers des automates temporisés. La construction que nous proposons est basée sur les testeurs temporels, une classe spécifique d'automates avec les entrées et les sorties qui réalisent la fonction séquentielle définie par la sémantique des opérateurs MITL. Nous montrons d'abord comment chaque formule MITL peut être exprimée avec six opérateurs basiques (trois opérateurs passés et trois futurs) et nous proposons une construction de testeurs temporels à partir de ces opérateurs. Les testeurs temporels pour des formules MITL arbitraires sont obtenus en composant ces testeurs élémentaires.<br />Finalement, nous développons une procédure pour la synthèse automatique de contrôleurs à partir des spécifications de haut niveau exprimées avec le fragment borné de metric temporal logic (MTL). Nous proposons une traduction des propriétés spécifiées dans cette logique temporisée vers des automates temporisés déterministes, en supposant la variabilité bornée. Ensuite, nous pouvons appliquer à ces automates les algorithmes habituels de synthèse de sûreté pour construire un contrôleur qui satisfait la spécification par construction.

<p>Microelectronics is heading towards larger and larger systems implemented on a single chip. In wireless communication equipment, e.g., cellular phones, handheld computers etc., both analog and digital circuits are required. If several integrated circuits (ICs) are used in a system, a large amount of the power is consumed by the communication between the ICs. Furthermore, the communication between ICs is slow compared with on-chip communication. Therefore, it is favorable to integrate the whole system on a single chip, which is the objective in the system-on-chip (SoC) approach.</p><p>In a mixed-signal SoC, analog and digital circuits share the same chip. When digital circuits are switching, they produce noise that is spread through the silicon substrate to other circuits. This noise is known as substrate noise. The performance of sensitive analog circuits is degraded by the substrate noise in terms of, e.g., lower signal-to-noise ratio and lower spurious-free dynamic range. Another problem is the design of the clock distribution net, which is challenging in terms of obtaining low power consumption, sharp clock edges, and low simultaneous switching noise.</p><p>In this thesis, a noise reduction strategy that focus on reducing the amount of noise produced in digital clock buffers, is presented. The strategy is to use a clock with long rise and fall times. It is also used to relax the constraints on the clock distribution net, which also reduce the design effort. Measurements on a test chip show that the strategy can be implemented in an IC with low cost in terms of speed and power consumption. Comparisons between substrate coupling in silicon-on-insulator (SOI) and conventional bulk technology are made using simple models. The objective here is to get an understanding of how the substrate coupling differs in SOI from the bulk technology. The results show that the SOI has less substrate coupling when no guard band is used, up to a certain frequency that is highly dependent of the chip structure. When a guard band is introduced in one of the analyzed test structures, the bulk resulted in much higher attenuation compared with SOI. An on-chip measurement circuit aiming at measuring simultaneous switching noise has also been designed in a 0.13 µ SOI process.</p> / Report code: LiU-Tek-Lic-2005:33.

In many consumer products, e.g., cellular phones and handheld computers, both digital and analog circuits are required. Nowadays, it is possible to implement a large subsystem or even a complete system, that earlier required several chips, on a single chip. A system on chip (SoC) has generally the advantages of lower power consumption and a smaller fabrication cost compared with multi-chip solutions. The switching of digital circuits generates noise that is injected into the silicon substrate. This noise is known as substrate noise and is spread through the substrate to other circuits. The substrate noise received in an analog circuit degrades the performance of the circuit. This is a major design issue in mixed-signal ICs where analog and digital circuits share the same substrate. Two new noise reduction methods are proposed in this thesis work. The first focuses n reducing the switching noise generated in digital clock buffers. The strategy is to use a clock with long rise and fall times in conjunction with a special D flip-flop. It relaxes the constraints on the clock distribution net, which also reduce the design effort. Measurements on a test chip implemented in a 0.35 μm CMOS technology show that the method can be implemented in an IC with low cost in terms of speed and power consumption. A noise reduction up to 50% is obtained by using the method. The measured power consumption of the digital circuit, excluding the clock buffer, increased 14% when the rise and fall times of the clock were increased from 0.5 ns to 10 ns. The corresponding increase in propagation delay was less than 0.5 ns corresponding to an increase of 50% in propagation delay of the registers. The second noise reduction method focuses on reducing simultaneous switching noise below half the clock frequency. This frequency band is assumed to be the signal band of an analog circuit. The idea is to use circuits that have as close to periodic power supply currents as possible to obtain low simultaneous switching noise below the clock in the frequency domain. For this purpose we use precharged differential cascode switch logic together with a novel D flip-flop. To evaluate the method two pipelined adders have been implemented on transistor level in a 0.13 μm CMOS technology, where the novel circuit is implemented with our method and the reference circuit with static CMOS logic together with a TSPC D flip-flop. According to simulation results, the frequency components in the analog signal band can be attenuated from 10 dB up to 17 dB using the proposed method. The cost is mainly an increase in power consumption of almost a factor of three. Comparisons between substrate coupling in silicon-on-insulator (SOI) and conventional bulk technology are made using simple models. The objective is to get an understanding of how the substrate coupling differs in SOI from the bulk technology. The results show that the SOI has less substrate coupling if no guard band is used, up to a certain frequency that is dependent of the test case. Introducing a guard band resulted in a higher attenuation of substrate noise in bulk than in SOI. An on-chip measurement circuit aiming at measuring simultaneous switching noise has been designed in a 0.13 μm SOI CMOS technology. The measuring circuit uses a single comparator per channel where several passes are used to capture the waveform. Measurements on a fabricated testchip indicate that the measuring circuit works as intended. A small part of this thesis work has been done in the area of digit representation in digital circuits. A new approach to convert a number from two’s complement representation to a minimum signed-digit representation is proposed. Previous algorithms are working either from the LSB to the MSB (right-to-left) or from the MSB to the LSB (left-to-right). The novelty in the proposed algorithm is that the conversion is done from left-to-right and right-to-left concurrently. Using the proposed algorithm, the critical path in a conversion circuit can be nearly halved compared with the previous algorithms. The area and power consumption, of the implementation of the proposed algorithm, are somewhere between the left-to-right and right-to-left implementations. / Articles I, II, III, IV, VII and IX are published with permisson from IEEE dated 07/05/18. Copyright IEEE.

The miniaturization and digitization of modern microelectronic systems have made Analog-to-Digital converters (ADC) key building components in many applications. Internet and entertainment technologies demand higher and higher performance from the hardware components in many communication and multimedia systems, but at the same time increased mobility demands less and less power consumption. Many applications, such as instrumentation, video, radar and communications, require very high accuracy and speed and with resolutions up to 16 bits and sampling rates in the 100s of MHz, pipelined ADCs are very suitable for such purposes. Resolutions above 10 bits often require very high power consumption and silicon area if no error correction technique is employed. Calibration relaxes the accuracy requirement of the individual building blocks of the ADC and enables power and area savings. Digital calibration is preferred over analog calibration due to higher robustness and accuracy. Furthermore, the microprocessors that process the digital information from the ADCs have constantly reduced cost and power consumption and improved performance due to technology scaling and innovative microprocessor architectures. The work in this dissertation presents a novel digital background calibration technique for high-speed, high-resolution pipelined ADCs. The technique is implemented in a 14 bit, 100 MS/s pipelined ADC fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.13µm Complementary Metal Oxide Semiconductor (CMOS) digital technology. The prototype ADC achieves better than 11.5 bits linearity at 100 MS/s and achieves a best-in-class figure of merit of 360 fJ/conversion-step. The core ADC has a power consumption of 105 mW and occupies an active area of 1.25 mm^2. The work in this dissertation also presents a low-power, 8-bit algorithmic ADC. This ADC reduces power consumption at system level by minimizing voltage reference generation and ADC input capacitance. This ADC is implemented in International Business Machines Corporation (IBM) 90nm digital CMOS technology and achieves around 7.5 bits linearity at 0.25 MS/s with a power consumption of 300 µW and an active area of 0.27 mm^2.

The advent of high-frequency silicon-based technologies has enabled the design of mixed-signal circuits that incorporate analog, RF, and digital circuit components to build cost-effective system-on-a-chip solutions. Emerging applications provide great incentive for continued scaling of transistor performance, requiring careful attention to mismatch, noise, and reliability concerns. If these mixed-signal technologies are to be employed within space-based electronic systems, they must also demonstrate reliability in radiation-rich environments. SiGe BiCMOS technology in particular is positioned as an excellent candidate to satisfy all of these requirements. The objective of this research is to develop predictive modeling tools that can be used to design new mixed-signal technologies and assess their reliability on Earth and in extreme environments. Ultimately, the goal is to illuminate the interaction of device- and circuit-level reliability mechanisms and establish best practices for modeling these effects in modern circuits. To support this objective, several specific areas have been targeted first, including a TCAD-based approach to identify performance-limiting regions in SiGe HBTs, measurement and modeling of carrier transport parameters that are essential for predictive TCAD, and measurement of device-level single-event transients to better understand the physical origins and implications for device design. These tasks provide the foundation for the bulk of this research, which addresses circuit-level reliability challenges through the application of novel mixed-mode TCAD techniques. All of the individual tasks are tied together by a guiding theme: to develop a holistic understanding of the challenges faced by emerging broadband technologies by coordinating results from material, device, and circuit studies.

Mixed-signal designs are becoming more and more complex every day. In order to adapt to the new market requirements, a formal process for design and verification of mixed signal systems i. e. top-down design and bottom-up verification methodology is required. This methodology has already been established for digital design. The goal of this research is to propose a new design methodology for mixed signal systems. In the first two chapters of this thesis, the need for a mixed signal design flow based on top-down design methodology will be discussed. The proposed design flow is based on behavioral modeling of the mixed signal system using one of the mixed signal behavioral modeling languages. These models can be used for design and verification through different steps of the design from system level modeling to final physical design. The other advantage of the proposed flow is analog and digital co-design. In the remaining chapters of this thesis, the proposed design flow was verified by designing an 800 MHz mixed signal PLL. The PLL uses a charge pump phase frequency detector, a single capacitor loop filter, and a feed forward error correction architecture using an active damping control circuit instead of passive resistor in loop filter. The design was done in 0. 18- <i>µ</i> m CMOS process technology.

Tests for detecting faults in analog and mixed-signal circuits have been traditionally derived from the datasheet speci and #64257;cations. Although these speci and #64257;cations describe important aspects of the device, in many cases these application oriented tests are costly to implement and are inefficient in determining product quality. Increasingly, the gap between speci and #64257;cation test requirements and the capabilities of test equipment has been widening. In this work, a systematic method to generate and evaluate alternate tests for detecting parametric faults is proposed. We recognize that certain aspects of analog test generation problem are not amenable to automation. Additionally, functional features of analog circuits are widely varied and cannot be assumed by the test generator. To overcome these problems, an extended device under test (DUT) model is developed that encapsulates the DUT and the DUT speci and #64257;c tasks. The interface of this model provides a well de and #64257;ned and uniform view of a large class of devices. This permits several simpli and #64257;cations in the test generator. The test generator is uses a search-based procedure that requires evaluation of a large number of candidate tests. Test evaluation is expensive because of complex fault models and slow fault simulation techniques. A tester-resident test evaluation technique is developed to address this issue. This method is not limited by simulation complexity nor does it require an explicit fault model. Making use of these two developments, an efficient and automated test generation method is developed. Theoretical development and a number of examples are used to illustrate various concepts that are presented in this thesis.