Este trabalho propõe o desenvolvimento de uma metodologia para a verificação circuitos integrados de sinais mistos de uso em sistemas de comunicação que operem em modo simplex. Deseja-se aproveitar as características inversas de recepção e transmissão para otimizar o processo de verificação. Para o desenvolvimento desta metodologia de verificação, teve-se como objetivo estudar metodologias de verificação de circuitos integrados de sinais mistos existentes e sua evolução, as quais têm garantido cada vez mais a funcionalidade de circuitos integrados que são compostos por blocos analógicos e digitais. A metodologia é aplicada a um dos circuitos que compõem um sistema otimizado de transmissão de dados via satélite (Transponder para Satélite). O sistema de transmissão de dados via satélite, foco do trabalho, é composto por receptores, transmissores e conversores analógico digital e um Processador Digital de Sinais - Digital Signal Processing (DSP), todos desenvolvidos em hardware. A metodologia de verificação compreende no desenvolvimento de uma estrutura de verificação capaz de estimular os blocos digitais e analógicos com o objetivo de garantir a funcionalidade de cada um dos componentes do IP Transponder. Em uma etapa seguinte, foi possível estimular o IP Transponder de forma integrada, no que se refere aos os blocos digitais e analógicos, assim como os de transmissão e recepção. Ressalta-se ainda que todo o desenvolvimento foi realizado em alto nível, ou seja, todas as características e propriedades foram observadas utilizando-se somente simuladores para garantir a funcionalidade do circuito integrado de sinais mistos que compõe o IP Transponder para satélite. / This work proposes the development of a verification methodology, used during the verification process of a mixed signal integrated circuit, which represents a communication system operating in simplex mode. In order to optimize the verification process, reverse reception and transmission will be used. With the intention of developing our verification methodology, a study on other methodologies used for the verification of mixed signals integrated circuits and the evolution of such methodologies was carried out. The proposed methodology has been applied in an advanced circuit used to establish data transmission by satellite (Transponder for Satellite). The targeted data transmission system is composed by analog receptor and transmitter, analog to digital converters and a digital signal-processing unit, all developed in hardware. The verification methodology consists of two steps: first, the development of a verification structure that are able to stimulate digital and analog blocks in order to guarantee the functionality of each system component. In a following step, the developed verification environment provides the stimulation for all the Transponder IP (digital and analog blocks), and for transmission and reception blocks as well. The verification process development was performed in high level, meaning all the characteristics and properties has been observed using only simulators with the purpose of guarantee the functionality of the mixed signal integrated circuit that composes the satellite Transponder IP.

In recent years, neuromorphic architectures have been an increasingly effective tool used to solve big data problems. Hardware neural networks have not been able to fully exploit the power efficient properties of the neural paradigm, however, due to limitations in standard CMOS. One of the largest challenges is the quadratic scaling of the synapses in a neural network. There has been some work in using post CMOS technology as synapses to overcome this limitation, but systems to date have not been scalable due to the design of their neurons. This dissertation aims to design and build scalable neural network architectures that can use emerging resistive memory technology as synapses. Using analog computing techniques to build networks is promising, especially due to the development of dense, CMOS compatible analog resistive memories. Building functional analog networks in advanced technology nodes, however, is challenging due to the relatively poor performance of analog components in these nodes. This work explores oscillatory neural networks (ONNs), which use phase as the analog state variable instead of voltage or current, reducing the number of traditional analog components required and making the networks better-suited for advanced nodes. This thesis develops additional ONN theory with regard to hardware networks, since previous work did not consider the effect of transmission delay on network dynamics. Transmission delay is proven to cause desynchronization in unmodified ONNs, and the theoretical analysis suggests ways to build networks which do synchronize. Conclusions from the theoretical development are used to build a PLL-based ONN in hardware. The PLL-based ONN is more energy efficient than comparable systems implemented in digital CMOS, although the neuron area is somewhat larger. The measurement of the PLL-based ONN also reveals additional poorly-studied facets of ONN dynamics. Using the knowledge gained from the PLL-based ONN, a larger, PLL-free ONN is built in the same technology. Removing the PLL in each neuron reduces the power and area consumption without sacrificing any functionality.This dissertation demonstrates that ONNs are well-suited to take advantage of emerging resistive memory technology to build efficient hardware neural networks.

New circuit design techniques that accommodate lower supply voltages necessary for portable systems need to be integrated into the semiconductor intellectual property (IP) core. Systems that once worked at 3.3 V or 2.5 V now need to work at 1.8 V or lower, without causing any performance degradation. Also, the fluctuation of device characteristics caused by process variation in nanometer technologies is seen as design yield loss. The numerous parasitic effects induced by layouts, especially for high-performance and high-speed circuits, pose a problem for IC design. Lack of exact layout information during circuit sizing leads to long design iterations involving time-consuming runs of complex tools. There is a strong need for low-power, high-performance, parasitic-aware and process-variation-tolerant circuit design. This dissertation proposes methodologies and techniques to achieve variability, power, performance, and parasitic-aware circuit designs. Three approaches are proposed: the single iteration automatic approach, the hybrid Monte Carlo and design of experiments (DOE) approach, and the corner-based approach. Widely used mixed-signal circuits such as analog-to-digital converter (ADC), voltage controlled oscillator (VCO), voltage level converter and active pixel sensor (APS) have been designed at nanoscale complementary metal oxide semiconductor (CMOS) and subjected to the proposed methodologies. The effectiveness of the proposed methodologies has been demonstrated through exhaustive simulations. Apart from these methodologies, the application of dual-oxide and dual-threshold techniques at circuit level in order to minimize power and leakage is also explored.

Parmi les produits électroniques de l’industrie des semi-conducteurs, les applications mixtes numériques-analogiques (AMS) représentent une part de marché à forte croissance. Le principal problème pour la conception de systèmes AMS est l’absence de flot de conception standard, puisque les blocs AMS ne peuvent pas être synthétisés de façon systématique `a partir d’une spécification de haut niveau en l’absence d’information au niveau transistor. Par ailleurs, il est très difficile de modéliser les caractéristiques au niveau transistor dans des descriptions comportementales de plus haut niveau (système). Face à ces d´défis, nous proposons une plateforme de modélisation, de dimensionnement et de vérification unifiée. La plate-forme repose sur une méthode de dimensionnement ascendant des blocs analogiques et une approche de simulation descendante depuis le système jusqu’aux transistors. Les différents niveaux d’abstraction envisagés sont d´écrits grâce aux langages C/C ++ et SystemC-AMS. En outre, nous expliquons comment UVM-SystemC-AMS développé dans le cadre du projet européen FP7 VERDI, fournit une m´méthode pour la vérification des systèmes AMS avec des interactions HW / SW. Nous appliquons ces méthodes à deux circuits. Le premier est un circuit de conversion analogique numérique pipeline à 3 étages et 6 bits. Il présente une vue hiérarchique du processus de conception. Le second est un sous-système analogique d’un système implantable de télémétrie, qui inclut une boucle de rétroaction. / Mixed-signal applications are among the fastest growing market segments in the electronics and semiconductor industry. This is driven by the growth opportunities in mobile communication, networking, power management, automotive, medical, imaging, and security applications, which all require analog and mixed-signal (AMS) content. One bottleneck exists if the designs include analog components together with digital ones. Digital design has a well-defined, top-down design methodology, but AMS design has traditionally been an ad hoc custom design process, it is more time-consuming interactive process and fully based on designerÕs expertise. The major difficulty is how to model the impact of circuit non-idealities and technology process variations on system- level performances.In this thesis, we present an unified modeling, design and verification platform with a fast sizing and biasing methodology. The proposed methodology propagates the circuit-level non- idealities into system-level simulations in a very natural way. The methodology synchronizes SystemC-AMS TDF MoC and electrical circuit simulator (SPICE), which enables to mix non- conservative system-level model with conservative nonlinear circuit netlist. Besides, we explain how UVM-SystemC-AMS developed in the FP7 Verdi project, provides an unified methodology for the verification of systems having interconnected AMS, HW/SW. In order to explore the effectiveness of the proposed methodology, two case studies are investigated: a 3-stage 6-bit ADC pipeline and a voltage regulator for an implantable telemetric system. The problem of hierarchical design is illustrated in the 3-stage 6-bit ADC pipeline while the problem of system architecture with feedback loop is illustrated in the implantable telemetric system.

Indiana University-Purdue University Indianapolis (IUPUI) / Recent ULSI (ultra large scale integration) technology emphasizes small size devices, featuring low power and high switching speed. Moore's law has been followed successfully in scaling down the silicon device in order to enhance the level of integration with high performances until conventional devices failed to cop up with further scaling due to limitations with ballistic effects, and challenges with accommodating dopant fluctuation, mobility degradation, among other device parameters. Recently, Graphene based devices o ered alternative approach, featuring small size and high performances. This includes high carrier mobility, high carrier density, high robustness, and high thermal conductivity. These unique characteristics made the Graphene devices attractive for high speed electronic architectures. In this research, Graphene devices were integrated into applications with analog, digital, and mixed signals based systems. Graphene devices were briefly explored in electronics applications since its first model developed by the University of Illinois, Champaign in 2013. This study emphasizes the validation of the model in various applications with analog, digital, and mixed signals. At the analog level, the model was used for voltage and power amplifiers; classes A, B, and AB. At the digital level, the device model was validated within the universal gates, adders, multipliers, subtractors, multiplexers, demultiplexers, encoders, and comparators. The study was also extended to include Graphene devices for serializers, the digital systems incorporated into the data structure storage. At the mixed signal level, the device model was validated for the DACs/ADCs. In all components, the features of the new devices were emphasized as compared with the existing silicon technology. The system functionality and dynamic performances were also elaborated. The study also covered the linearity characteristics of the devices within full input range operation. GNRFETs with a minimum channel length of 10nm and an input voltage 0.7V were considered in the study. An electronic design platform ADS (Advanced Design Systems) was used in the simulations. The power amplifiers showed noise figure as low as 0.064dbs for class A, and 0.32 dbs for class B, and 0.69 dbs for class AB power amplifiers. The design was stable and as high as 5.12 for class A, 1.02 for class B, and 1.014 for class AB. The stability factor was estimated at 2GHz operation. The harmonics were as low as -100 dbs for class A, -60 dbs for class B, and -50dbs for class AB, all simulated at 1GHz. The device was incorporated into ADC system, and as low as 24.5 micro Watt power consumption and 40 nsec rise time were observed. Likewise, the DAC showed low power consumption as of 4.51 micro Watt. The serializer showed as minimum power consumption of the order of 0.4mW. These results showed that these nanoscale devices have potential future for high-speed communication systems, medical devices, computer architecture and dynamic Nano electromechanical (NEMS) which provides ultra-level of integration, incorporating embedded and IoT devices supporting this technology. Results of analog and digital components showed superiority over other silicon transistor technologies in their ultra-low power consumption and high switching speed.

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MOS current mode logic (MCML) offers low noise digital circuits that reduce noise that can cripple analog components in mixed-signal integrated circuits, when compared to CMOS digital circuits. An MCML standard cell library was developed for the Cadence Virtuoso Integrated Circuit (IC) design software that gives IC designers the ability to design complex, low noise digital circuits for use in mixed-signal and noise sensitive systems at a high level of abstraction, allowing them to get superior products to market faster than competitors. The MCML standard cell library developed and presented here allows for fast development of mixed signal circuits by providing quiet digital building block gates that reduce the simultaneous switching noise (SSN) by an order of magnitude over conventional CMOS based designs [3]. This thesis project developed the following digital gates in MCML as a standard cell library for general-purpose low noise and very low noise applications: inverter, buffer, NAND, AND, NOR, OR, XOR, NXOR, 2:1 MUX, CMOS to MCML, MCML to CMOS, and double edge triggered flip-flop (DETFF).

Bioelectronics effectively bridges the gap between the biochemical and the electrical domains, integrating aspects of biology, electronics, physics, and material science to foster innovative solutions and impact the trajectory of human health and environmental science, by translating biological responses into electrical signals for advanced analysis. Despite its transformative potential, current bioelectronic systems face limitations in terms of scalability, sensitivity, and ease of integration. This thesis claims that co-designing Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits with highly specific and sensitive genetically engineered biosensors is pivotal in bioelectronics evolution, offering high accuracy, reliability, miniaturization, and multiplexed sensing capabilities essential for addressing challenges in healthcare, environmental monitoring, sustainable manufacturing, and beyond. To support this claim, this dissertation highlights two key contributions: a low-power ingestible sensor for gastrointestinal tract monitoring and a hybrid platform technology combining droplet microfluidics and CMOS electronics for impedance spectroscopy and luminescence sensing for rapid screening and optimization of biosensors under different environmental conditions. The first contribution details an ingestible capsule that could transform healthcare diagnostics through a novel threshold-crossing-based detector and CMOS-integrated photodiodes. This innovation exemplifies how hybrid bioelectronic systems can significantly improve the precision and non-invasiveness of real-time health monitoring. Moving beyond the traditional scope of bioelectronics and the sole purpose of health monitoring, the second contribution extends its application by integrating droplet microfluidics with CMOS chips, facilitating high-throughput droplet screening to optimize biosensor performance for application deployment. To achieve this goal, this platform is equipped with a low-noise, high-resolution CMOS impedance spectroscopy chip and a high-resolution CMOS luminescence detector chip. In highlighting these contributions, the thesis reinforces the assertion that hybrid bioelectronic systems are key to addressing a wide range of societal challenges. Moreover, the integration of synthetic biology and microfluidics with CMOS technology, as demonstrated in this work, not only overcomes existing barriers, such as achieving miniaturization, high sensitivity, rapid data processing, and energy efficiency, but also paves the way for future innovations with extensive potential in personalized medicine and environmental sustainability. / 2026-01-17T00:00:00Z

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