With the current demand for mixed-signal SoCs, an increasing number of designers are looking for ADC architectures that can be easily implemented over digital substrates. Since ADC performance is strongly dependent upon physical and electrical features, it gets more difficult for them to benefit from more recent technologies, where these features are more variable. This way, analog signal acquisition is not allowed to follow an evolutionary trend compatible with Moore’s Law. In fact, such trend shall get worst, since newer technologies are expected to have more variable characteristics. Also, for a matter of economy of scale, many times a mixed-signal SoC presents a good amount of idle processing power. In such systems it is advantageous to employ more costly digital signal processing provided that it allows a reduction in the analog area demanded or the use of less expensive analog blocks, able to cope with process variations and uncertainty. Besides the technological concerns, other factors that impact the cost of the design also advise to transfer problems from the analog to the digital domain whenever possible: design automation and self-test requirements, for instance. Recent surveys indicate that the total cost in designer hours for the analog blocks of a mixed-signal system can be up to three times the cost of the digital ones. This manuscript explores the concept of bottom-up analog acquisition design, using statistical sampling as a way to reduce the analog area demanded in the design of ADCs within mixed-signal systems. More particularly, it investigates the possibility of using digital modeling and digital compensation of non-idealities to ease the design of ADCs. The work is developed around three axes: the definition of target applications, the development of digital compensation algorithms and the exploration of architectural possibilities. New methods and architectures are defined and validated. The main notions behind the proposal are analyzed and it is shown that the approach is feasible, opening new paths of future research. Keywords:

High-speed and high-resolution digital-to-analog converters (DACs) are vital components in all telecommunication systems. Radio-frequency digital-to-analog converter (RFDAC) provides high-speed and high-resolution conversion from digital domain to an analog signal. RFDACs can be employed in direct-conversion radio transmitter architectures. The idea of RFDAC is to utilize an oscillatory pulse-amplitude modulation instead of the conventional zero-order hold pulse amplitude modulation, which results in DAC output spectrum to have high energy high-frequency lobe, other than the Nyquist main lobe. The frequency of the oscillatory pulse can be chosen, with respect to the sample frequency, such that the aliasing images of the signal at integer multiples of the sample frequency are landed in the high-energy high-frequency lobes of the DAC frequency response. Therefore the high-frequency images of the signal can be used as the output of the DAC, i.e., no need to the mixing stage for frequency up-conversion after the DAC in the radio transmitter. The mixing stage however is not eliminated but it is rather moved into the DAC elements and therefore the local oscillator (LO) signal with high frequency should be delivered to each individual DAC element. In direct-conversion architecture of IQ modulators which utilize the RFDAC technique, however, there is a problem of finite image rejection. The origin of this problem is the different polarity of the spectral response of the oscillatory pulse-amplitude modulation in I and Q branches. The conditions where this problem can be alleviated in IQ modulator employing RFDACs is also discussed in this work. ΣΔ modulators are used preceding the DAC in the transmitter chain to reduce the digital signal’s number of bits, still maintain the same resolution. By utilizing the ΣΔ modulator now the total number of DAC elements has decreased and therefore the delivery of the high-frequency LO signal to each DAC element is practical. One of the costs of employing ΣΔ modulator, however, is a higher quantization noise power at the output of the DAC. The quantization noise is ideally spectrally shaped to out-of-band frequencies by the ΣΔ modulator. The shaped noise which usually has comparatively high power must be filtered out to fulfill the radio transmission spectral mask requirement. Semi-digital FIR filter can be used in the context of digital-to-analog conversion, cascaded with ΣΔ modulator to filter the out-of-band noise by the modulator. In the same time it converts the signal from digital domain to an analog quantity. In general case, we can have a multi-bit, semi-digital FIR filter where each tap of the filter is realized with a sub-DAC of M bits. The delay elements are also realized with M-bit shift registers. If the output of the modulator is given by a single bit, the semi-digital FIR filter taps are simply controlled by a single switch assuming a current-steering architecture DAC. One of the major advantages is that the static linearity of the DAC is optimum. Since there are only two output levels available in the DAC, the static transfer function, regardless of the mismatch errors, is always given by a straight line. In this work, the design of SDFIR filter is done through an optimization procedure where the ΣΔ noise transfer function is also taken into account. Different constraints are defined for different applications in formulation of the SDFIR optimization problem. For a given radio transmitter application the objective function can be defined as, e.g., the hardware cost for SDFIR implementation while the constraint can be set to fulfill the radio transmitter spectral emission mask.

With the current demand for mixed-signal SoCs, an increasing number of designers are looking for ADC architectures that can be easily implemented over digital substrates. Since ADC performance is strongly dependent upon physical and electrical features, it gets more difficult for them to benefit from more recent technologies, where these features are more variable. This way, analog signal acquisition is not allowed to follow an evolutionary trend compatible with Moore’s Law. In fact, such trend shall get worst, since newer technologies are expected to have more variable characteristics. Also, for a matter of economy of scale, many times a mixed-signal SoC presents a good amount of idle processing power. In such systems it is advantageous to employ more costly digital signal processing provided that it allows a reduction in the analog area demanded or the use of less expensive analog blocks, able to cope with process variations and uncertainty. Besides the technological concerns, other factors that impact the cost of the design also advise to transfer problems from the analog to the digital domain whenever possible: design automation and self-test requirements, for instance. Recent surveys indicate that the total cost in designer hours for the analog blocks of a mixed-signal system can be up to three times the cost of the digital ones. This manuscript explores the concept of bottom-up analog acquisition design, using statistical sampling as a way to reduce the analog area demanded in the design of ADCs within mixed-signal systems. More particularly, it investigates the possibility of using digital modeling and digital compensation of non-idealities to ease the design of ADCs. The work is developed around three axes: the definition of target applications, the development of digital compensation algorithms and the exploration of architectural possibilities. New methods and architectures are defined and validated. The main notions behind the proposal are analyzed and it is shown that the approach is feasible, opening new paths of future research. Keywords:

Orientador: Nobuo Oki / Banca: Suely Cunha Amaro Mantovani / Banca: Jozué Vieira Filho / Banca: Marcelo Arturo Jara Perez / Banca: Paulo Augusto Dal fabbro / Resumo: Nesta tese, propõe-se um sintetizador de freqüência baseado em phase locked loops (PLL) usando uma arquitetura que utiliza um dual-path loop filter, constituído de componentes passivos e um integrador digital. A proposta é empregar técnicas digitais, para reduzir o custo da implementação do sintetizador de freqüência, e flexibilizar o projeto do loop filter, para possibilitar que a arquitetura opere em uma faixa de freqüência larga de operação e com redução de tons espúrios. O loop filter digital é constituído de um contador crescente/ decrescente cujo clock é proveniente da amostragem da diferença de fase de entrada. As técnicas digitais aplicadas ao loop filter se baseiam em alterações da operação do contador, em tempos pré-estabelecidos, os quais são controlados digitalmente. Essas técnicas possibilitam reduzir o tempo de estabelecimento do PLL ao mesmo tempo em que problemas de estabilidade são resolvidos. No desenvolvimento da técnica de dual-path foi realizado o estudo de sua estabilidade, primeiramente, considerando a aproximação do PLL para um sistema linear e depois usando controle digital. Nesse estudo foram deduzidas as equações do sistema, no domínio contínuo e discreto, tanto para o projeto da estabilidade, quanto para descrever o comportamento do PLL. A metodologia top-down é usada no projeto do circuito integrado. As simulações em nível de sistema são usadas, primeiramente, para as criações das técnicas e posteriormente para a verificação do seu comportamento, usando modelos calibrados com os blocos projetados em nível de transistor. O circuito integrado é proposto para ser aplicado em identificação por rádio freqüência (RFID) na banda de UHF (Ultra High Frequency), usando multi-standard, e deve operar na faixa de 850 MHz a 1010 MHz. O sintetizador de freqüência foi projetado na tecnologia CMOS... (Resumo completo, clicar acesso eletrônico abaixo) / Abstract: In this thesis, a frequency synthesizers phase locked loops (PLL) based with an architecture that uses a dual-path loop filter consisting of passive components and a digital integrator are proposed. The objective is to employ digital techniques to reduce the implementation cost and get loop filter design flexibility to enable the architecture to have a large tuning range operation and spurious reduction. The digital loop filter is based in an up/down counter where the phase difference is sampled to generate the clock of the counter. The techniques applied in the digital path are based in digitally controlled changes in the counter operation in predefined time points. These techniques provide PLL settling time reductions whiling the stability issues are solved. The stability study of the proposed dual path has been developed. First the linear system approximation for the PLL has been assumed and then employing digital control. The continuous and discrete time equations of architecture were derived in that study applied to stability design as well as to describe the architecture behavior. The top-down methodology has been applied to the integrated circuit design. In the beginning, the system level simulations are used for the techniques creation and then the behavioral models that were calibrated with transistor level blocks are simulated. The application of the circuit is proposed to Radio Frequency Identification (RFID) using UHF (Ultra High Frequency) band for multi-standards application and will operate in range of 850 MHz to 1010 MHz. The proposed frequency synthesizer has been designed in the AMS 0.35 μm CMOS technology with 2V power supply. A 300 μs of settling time and 140 Hz of resolution was obtained in simulations. The proposed frequency synthesizer have low complexity and shown a reference noise suppression about 45.6 dB better than the conventional architecture / Doutor

With the current demand for mixed-signal SoCs, an increasing number of designers are looking for ADC architectures that can be easily implemented over digital substrates. Since ADC performance is strongly dependent upon physical and electrical features, it gets more difficult for them to benefit from more recent technologies, where these features are more variable. This way, analog signal acquisition is not allowed to follow an evolutionary trend compatible with Moore’s Law. In fact, such trend shall get worst, since newer technologies are expected to have more variable characteristics. Also, for a matter of economy of scale, many times a mixed-signal SoC presents a good amount of idle processing power. In such systems it is advantageous to employ more costly digital signal processing provided that it allows a reduction in the analog area demanded or the use of less expensive analog blocks, able to cope with process variations and uncertainty. Besides the technological concerns, other factors that impact the cost of the design also advise to transfer problems from the analog to the digital domain whenever possible: design automation and self-test requirements, for instance. Recent surveys indicate that the total cost in designer hours for the analog blocks of a mixed-signal system can be up to three times the cost of the digital ones. This manuscript explores the concept of bottom-up analog acquisition design, using statistical sampling as a way to reduce the analog area demanded in the design of ADCs within mixed-signal systems. More particularly, it investigates the possibility of using digital modeling and digital compensation of non-idealities to ease the design of ADCs. The work is developed around three axes: the definition of target applications, the development of digital compensation algorithms and the exploration of architectural possibilities. New methods and architectures are defined and validated. The main notions behind the proposal are analyzed and it is shown that the approach is feasible, opening new paths of future research. Keywords:

Abstract This thesis studies the methods to test mixed-signal devices and circuits on board and system level with embedded test instrumentation. The study is divided in three continuous sections, development of embedded test methods for discrete components, integration of test instruments on board level and development of test and health monitoring strategy for large scale system. The developed embedded test methods for mixed signal circuitry on board level are based on the standard for mixed signal test bus IEEE 1149.4. The standardized embedded test infrastructure is utilized for testing discrete components with emphasis on testing active components as diodes and transistors. The developed embedded tests are evaluated with PCOLA/SOQ method for manufacturing testing and also the usability of the tests is discussed. A solution for embedded mixed-signal test controller is presented with discussion of test communication and the possibilities of implementing embedded test control. The target in the development of the test control is to enable launch mixed signal tests on device remotely. The test controller is IEEE 1149.4 compatible and can generate and measure analog test signals while controlling boundary-scan enabled devices. The final section of the thesis focuses on an embedded test solution for aerospace bus system (MIL-STD-1553). Current solutions are based on testing the bus system during maintenance on ground. The developed test and monitoring method allows on-line monitoring of the bus to detect and locate possible defects which only occur during use of the aeroplane. / Tiivistelmä Väitöstyössä tutkittiin sekasignaalilaitteiden ja -piirien testausmenetelmiä levy- ja järjestelmätasolla hyödyntäen sulautettuja testilaitteita. Työ jakaantuu kolmeen osaan; sulautettujen testausmenetelmien kehitys diskreeteille komponenteille, testi-instrumenttien integrointi piirilevytasolle sekä testaus- ja kunnonmonitorointimenetelmän kehitys laajemmalle järjestelmälle. Sulautettujen testimenetelmien kehitys sekasignaalipiireille piirilevytasolla perustuu sekasignaalitestiväylän standardiin IEEE 1149.4. Standardoitua sulautettua testi-infrastruktuuria käytettiin diskreettien komponenttien testaukseen painottuen aktiivikomponentteihin, kuten diodeihin ja transistoreihin. Kehitetyt sulautetut testit on arvioitu PCOLA/SOQ menetelmällä, jota hyödynnetään tuotantotestauksen testikattavuuden arvioinnissa. Lisäksi testimenetelmien käytettävyyttä arvioitiin. Sulautettu sekasignaalilaitteiden testikontrollerin tavoite on käynnistää ja suorittaa sekasignaalitestejä laitteessa etäältä. Kehitetty testikontrolleri on IEEE 1149.4 yhteensopiva ja voi generoida ja mitata analogista testisignaalia sekä samanaikaisesti ohjata testiväylää. Lisäksi etätestauksen mahdollistavasta testikommunikaatiomenetelmiä arvioitiin kuten myös erilaisia toteutustasoja sulautetuille testimenetelmille. Laajemman järjestelmän kehityksessä tutkittiin sulautettua testausratkaisua lentokoneen väyläjärjestelmälle, joka perustuu standardiin MIL-STD-1553B. Nykyiset menetelmät perustuvat väyläjärjestelmän testaukseen huollon yhteydessä, mutta osa virheistä ilmenee vain käytön aikana. Kehitetty testaus- ja monitorointimenetelmä mahdollistaa käytönaikaisen jatkuvan virheiden monitoroinnin sekä niiden paikantamisen lennon aikana.

La boucle à verrouillage de phase est essentielle dans la génération et la synthèse de fréquence, présent dans les communications RF, l’instrumentation, les capteurs ainsi que beaucoup d’autres domaines. Il existe deux types de dispositifs: la PLL numérique et la PLL analogique. La PLL numérique est essentiellement utilisée dans le domaine de l’instrumentation et dans la génération d’horloge, où les fréquences sont relativement faibles. Quant à la PLL analogique, elle est plus utilisée dans les communications sans fil ainsi que dans les transmetteurs à haut débit, dont la fréquence de fonctionnement est de l’ordre du GHz. Etant donné qu’une PLL est au moins du second ordre, elle peut être sujette à une instabilité pouvant mener à un disfonctionnement du système. Ainsi la méthodologie de conception d’un tel système comporte plusieurs étapes : 1) modélisation linéaire, 2) modélisation comportemental, 3) simulation niveau transistor. Les simulations électriques du comportement transitoire d’une PLL sont très gourmandes en temps. En effet des calculs dont la complexité croit avec le facteur de division sont effectués à chaque itération du signal de référence. Cela constitue un frein technologique, et rend la conception d’une PLL très difficile. Cette thèse se focalise sur le modèle comportemental des PLL analogiques fonctionnant avec des pompes de charge commandées en tension, dont la caractéristique du temps de démarrage qui est hautement non linéaire et même des fois chaotique est sujet critique. L’objectif principal est d’établir une méthodologie de conception efficiente pour les PLL analogiques et leur caractérisation en utilisant la technique évènementielle. / The Charge-Pump Phase Locked Loop (CP-PLL) is a mixed-signal system and the important block for the frequency generation or frequency synthesis in radio frequency communications, instrumentations, metrology, sensors and so on. There are two types of devices: a full digital PLL and an analog PLL. The fully digital PLL is mainly used in instrumentation field and in clock and data recovery circuits where moderate frequency operation is used. For wireless communication or high data-rate optical transceiver analog CP-PLL is the most used architecture where the operating frequency is in the range of GHz. Since a PLL is at least a second order system, it is subjected to an instability that can lead to non-functional device. Thus, common design methodology contains several steps including i) Linear models ii) Behavioral modeling iii) and transistor level simulations. Electrical simulation (like SPICE) of the transient operation of PLL is time consuming and may take up to several weeks. In fact, the simulator must perform, for each time step of the reference signal, calculations where complexity increases with the division factor. This is known as technological bottleneck, designing a PLL at transistor level is very hard in a reasonable time. In this thesis the work is focused on the behavioral modeling of CP-PLL operating with voltage switched charge-pump (VSCP), where the characterization of its transient time “off-locking” and highly non-linear and even in chaotic mode remains a critical issue. The main objective is to establish a fast and efficient modeling and design methodology of high order CP-PLL and its characterization using the event driven technique.

Die vorliegende Arbeit behandelt den Entwurf eines ADCs nach dem sukzessiven Approximationsverfahren (SAR). Ausgehend von den Systemanforderungen erfolgt eine Ableitung der Spezifikation des zu entwerfenden ADCs. Theoretische Betrachtungen und Highlevelsimulationen in Matlab wählen die optimale Architektur der Einzelkomponenten - kapazitives DAC Array, Komparator, Ablaufsteuerung - aus. Die Implementation selbst findet für die Analogschaltungsteile auf Transistorebene und für die digitalen Komponenten auf RT-Ebene in VHDL statt. Sie bilden die Grundlage für die Realisierung des Layouts. In dem Zusammenhang stellt die Arbeit die gängigsten Matchingmethoden für elektronische Bauelemente vor. Abschließende PEX-Simulationen (parasitic Extraction) ermitteln die statischen (INL/DNL) wie dynamischen Kennwerte (SNR) des SAR-ADCs.:Abkürzungsverzeichnis iii Formelzeichen v 1 Einleitung 1 2 Grundlagen 2 2.1 Analog/Digital-Umsetzer 2 2.1.1 Umsetzungsverfahren 2 2.1.2 Statische Kennwerte 8 2.1.3 Dynamische Kennwerte 12 2.2 Technologie 17 2.2.1 Übersicht 17 2.2.2 MOS-Transistoren 17 2.2.3 Kapazitäten 18 2.2.4 Widerstände 18 2.3 Hardwarebeschreibungssprache 19 2.3.1 Übersicht 19 2.3.2 Zustandsautomat 19 2.3.3 Look-Ahead-Ausgang 20 3 Spezifikation 21 4 ADU-Topologie 23 4.1 Vorüberlegungen 23 4.1.1 Umsetzungsverfahren 23 4.1.2 Vergleich Widerstand/Kapazität 23 4.1.3 Differenziell Vs. Single-Ended 24 4.1.4 Kapazitätsarray 25 4.2 ADC High-Level Modell 30 4.2.1 Funktionsblöcke 30 4.2.2 Matlab/Simulink 31 4.2.3 Simulation 34 4.3 Parasitäre Effekte 37 4.3.1 Substratkapazität 37 4.3.2 Komparatoroffset 39 5 Schaltungsdesign & -simulation 41 5.1 Komparator 41 5.1.1 Spezifikation 41 5.1.2 Latch 41 5.1.3 Vorverstärker 43 5.1.4 Gesamtsystem 46 5.2 Schalter 46 5.2.1 Funktionsweise 46 5.2.2 Ladungseintrag 46 5.2.3 Dimensionierung & Simulation 47 5.3 Kapazitätsarray 51 5.4 SAR-Controller 51 5.4.1 Vorüberlegung 51 5.4.2 RTL Design 52 5.4.3 Simulation 55 5.4.4 Synthese 57 5.4.5 Optimierung 59 5.5 ADC (Toplevel) 59 5.5.1 Architektur 59 5.5.2 Simulation 61 6 Layout 64 6.1 Komparator 65 6.1.1 Vorverstärker 1 65 6.1.2 Vorverstärker 2 66 6.1.3 Dynamisches Latch 66 6.2 Transmission Gates 67 6.3 Kapazitätsarray 68 6.4 SAR-Controller 70 6.5 ADC (Toplevel) 70 6.6 PEX Simulation 72 6.6.1 Statischer Test 72 6.6.2 Dynamischer Test 73 7 Zusammenfassung 74 Literaturverzeichnis 76 Bücher 76 Skripte und Schriften 76 Internetlinks 78 Abbildungsverzeichnis 79 Tabellenverzeichnis 82 Anhang 84

Les stations de base à petite échelle (picocellules et femtocellules) seront un des leviers principaux qui permettront d'atteindre l'objectif 1000X, objectif fixé par les grands acteurs du domaine des télécommunications visant à augmenter la capacité des réseaux mobiles sans fil 5G d'un facteur 1000 par rapport aux réseaux 4G. Dans ce type de réseau, l'amplificateur de puissance (PA) est responsable de la majorité de la consommation de puissance de la station de base. Pour minimiser sa consommation de puissance, le PA est polarisé proche de sont point de compression mais avec l'augmentation des largeurs de bande, ce dernier subit des effets de mémoire accrus qui viennent s'ajouter aux problèmes classiques de non-linéarités. Les systèmes de prédistorsion numérique (DPD), et analogique/RF(ARFPD) peuvent être utilisés pour améliorer le compromis linéarité / efficacité des PAs. Cependant pour les pico-cellules et femto-cellules utilisées dans le standard 5G, les prédistorseurs conventionnels ne sont adaptés pour des raisons de complexité et de consommation de puissance.Le modèle "Memory Polynomilal" (MP) est l'un des modèles de prédistorsion les plus attractifs pour modéliser les PAs, fournissant des performances intéressantes avec peu de coefficients. Cependant, la précision de ce modèle se dégrade pour les signaux large bance. Pour palier ce problème, nous proposons un nouveau modèle, le FIR-MP qui combine un filtre FIR au modèle MP classique. Pour valider et quantifier la précision du modèle proposé, nous avons effectué des simulations avec un modèle extrait par mesure de l'amplificateur sur étagère ADL5606 (GaAs 1W HBT PA). Les résultats de ces simulations présentent des améliorations du taux de fuite des canaux adjacents (ACLR) de 7,2 dB et 15,6 dB, respectivement, pour des signaux à 20 MHz et 80 MHz par rapport au modèle MP classique. Le FIR-MP a été également synthétisé en technologie CMOS FDSOI 28 nm. Les résultats de la synthèse ont donné une puissance globale de 9,18 mW and 116,2 mW, respectivement, pour les signaux de 20 MHz and 80 MHz.Basé sur le modèle proposé de FIR-MP, une nouvelle approche à signaux mixtes pour linéariser les PAs a été aussi étudiée. En fait, le filtre numérique FIR améliore la performance de correction de la mémoire sans aucune expansion de la bande passante et la linéarisation en bande de base permet d'éviter l'utilisation de composants RF dans la linéariseur. Ainsi, les contraintes en bande passante requises pour le DAC, les filtres de reconstruction et les blocs RF de l'émetteur sont relâchées comparés aux techniques conventionnelles de linéarisation numériques et RF. Nous avons ainsi étudié l'impact des diverses non-idéalités en utilisant un signal modulé à 80 MHz afin de dériver les exigences pour la mise en œuvre du circuit. Les simulations ont montré qu'une résolution de 8 bits pour les coefficients et un SNR de 60 dB sont nécessaires pour atteindre un ACLR1 supérieur à 45 dBc. Ces résultats constituent un premier signe favorable dans l'optique d'une implémentation matérielle de la solution proposée, étape indispensable pour évaluer précisément sa consommation de puissance et sa complexité pour pouvoir la comparer à l'état de l'art des linéariseurs. / Small-cell base stations (picocells and femtocells) handling high bandwidths (> 100 MHz) will play a vital role in realizing the 1000X network capacity objective of the future 5G wireless networks. Power Amplifier (PA) consumes the majority of the base station power, whose linearity comes at the cost of efficiency. With the increase in bandwidths, PA also suffers from increased memory effects. Digital predistortion (DPD) and analog RF predistortion (ARFPD) tries to solve the linearity/efficiency trade-off. In the context of 5G small-cell base stations, the use of conventional predistorters becomes prohibitively power-hungry.Memory polynomial (MP) model is one of the most attractive predistortion models, providing significant performance with very few coefficients. We propose a novel FIR memory polynomial (FIR-MP) model which significantly augments the performance of the conventional memory polynomial predistorter. Simulations with models extracted on ADL5606 which is a 1 W GaAs HBT PA show improvements in adjacent channel leakage ratio (ACLR) of 7.2 dB and 15.6 dB, respectively, for 20 MHz and 80 MHz signals, in comparison with MP predistorter. Digital implementation of the proposed FIR-MP model has been carried out in 28 nm FDSOI CMOS technology. With a fraction of the power and die area of that of the MP a huge improvement in ACLR is attained.An overall estimated power consumption of 9.18 mW and 116.2 mW, respectively, for 20 MHz and 80 MHz signals is obtained.Based on the proposed FIR-MP model a novel low-power mixed-signal approach to linearize RF power amplifiers (PAs) is presented. The digital FIR filter improves the memory correction performance without any bandwidth expansion and the MP predistorter in analog baseband provides superior linearization. MSPD avoids 5X bandwidth requirement for the DAC and reconstruction filters of the transmitter and the power-hungry RF components when compared to DPD and ARFPD, respectively.The impact of various non-idealities is simulated with ADL5606 (1 W GaAs HBT PA) MP PA model using 80 MHz modulated signal to derive the requirements for the integrated circuit implementation. A resolution of 8 bits for the coefficients and a signal path SNR of 60 dB is required to achieve ACLR1 above 45 dBc, with as little as 9 coefficients in the analog domain. Discussion on the potential circuit architectures of subsystems is provided. It results that an analog implementation is feasible. It will be worth in the future to continue the design of this architecture up to a silicon prototype to evaluate its performance and power consumption.

A novel scheme of optimizing the individual components of a phase locked loop (PLL) which is used for stable clock generation and synchronization of signals is considered in this work. Verilog-A is used for the high level system design of the main components of the PLL, followed by the individual component wise optimization. The design of experiments (DOE) approach to optimize the analog, 45nm voltage controlled oscillator (VCO) is presented. Also a mixed signal analysis using the analog and digital Verilog behavior of components is studied. Overall a high level system design of a PLL, a systematic optimization of each of its components, and an analog and mixed signal behavioral design approach have been implemented using cadence custom IC design tools.