Les systèmes sur puces intègrent aujourd’hui sur le même substrat des parties analogiques et des unités de traitement numérique. Tandis que la complexité de ces systèmes s’accroissait, leur temps de mise sur le marché se réduisait. Une conception descendante globale et coordonnée du système est devenue indispensable de façon à tenir compte des interactions entre les parties analogiques et les partis numériques dès le début du développement. Dans le but de répondre à ce besoin, cette thèse expose un processus de raffinement progressif et méthodique des parties analogiques, comparable à ce qui existe pour le raffinement des parties numériques. L'attention a été plus particulièrement portée sur la définition des niveaux analogiques les plus abstraits et à la mise en correspondance des niveaux d’abstraction entre parties analogiques et numériques. La cohérence du raffinement analogique exige de détecter le niveau d’abstraction à partir duquel l’utilisation d’un modèle trop idéalisé conduit à des comportements irréalistes et par conséquent d’identifier l’étape du raffinement à partir de laquelle les limitations et les non linéarités aux conséquences les plus fortes sur le comportement doivent être introduites. Cette étape peut être d’un niveau d'abstraction élevé. Le choix du style de modélisation le mieux adapté à chaque niveau d'abstraction est crucial pour atteindre le meilleur compromis entre vitesse de simulation et précision. Les styles de modélisations possibles à chaque niveau ont été examinés de façon à évaluer leur impact sur la simulation. Les différents modèles de calcul de SystemC-AMS ont été catégorisés dans cet objectif. Les temps de simulation obtenus avec SystemC-AMS ont été comparés avec Matlab Simulink. L'interface entre les modèles issus de l'exploration d'architecture, encore assez abstraits, et les modèles plus fin requis pour l'implémentation, est une question qui reste entière. Une bibliothèque de composants électroniques complexes décrits en SystemC-AMS avec le modèle de calcul le plus précis (modélisation ELN) pourrait être une voie pour réussir une telle interface. Afin d’illustrer ce que pourrait être un élément d’une telle bibliothèque et ainsi démontrer la faisabilité du concept, un modèle d'amplificateur opérationnel a été élaboré de façon à être suffisamment détaillé pour prendre en compte la saturation de la tension de sortie et la vitesse de balayage finie, tout en gardant un niveau d'abstraction suffisamment élevé pour rester indépendant de toute hypothèse sur la structure interne de l'amplificateur ou la technologie à employer. / Systems on Chip (SoC) embed in the same chip analogue parts and digital processing units. While their complexity is ever increasing, their time to market is becoming shorter. A global and coordinated top-down design approach of the whole system is becoming crucial in order to take into account the interactions between the analogue and digital parts since the beginning of the development. This thesis presents a systematic and gradual refinement process for the analogue parts comparable to what exists for the digital parts. A special attention has been paid to the definition of the highest abstracted analogue levels and to the correspondence between the analogue and the digital abstraction levels. The analogue refinement consistency requires to detect the abstraction level where a too idealised model leads to unrealistic behaviours. Then the refinement step consist in introducing – for instance – the limitations and non-linearities that have a strong impact on the behaviour. Such a step can be done at a relatively high level of abstraction. Correctly choosing a modelling style, that suits well an abstraction level, is crucial to obtain the best trade-off between the simulation speed and the accuracy. The modelling styles at each abstraction level have been examined to understand their impact on the simulation. The SystemC-AMS models of computation have been classified for this purpose. The SystemC-AMS simulation times have been compared to that obtained with Matlab Simulink. The interface between models arisen from the architectural exploration – still rather abstracted – and the more detailed models that are required for the implementation, is still an open question. A library of complex electronic components described with the most accurate model of computation of SystemC-AMS (ELN modelling) could be a way to achieve such an interface. In order to show what should be an element of such a library, and thus prove the concept, a model of an operational amplifier has been elaborated. It is enough detailed to take into account the output voltage saturation and the finite slew rate of the amplifier. Nevertheless, it remains sufficiently abstracted to stay independent from any architectural or technological assumption.

La bioélectronique est un domaine transdisciplinaire qui oeuvre, entre autres, àl’interconnexion entre des systèmes biologiques présentant une activité électrique et le mondede l’électronique. Cette communication avec le vivant implique l’observation de l’activitéélectrique des cellules considérées et nécessite donc une chaine d’acquisition électronique.L’utilisation de Multi/Micro Electrodes Array débouche sur des systèmes devantacquérir un grand nombre de canaux en parallèle, dès lors la consommation etl’encombrement des circuits d’acquisition ont un impact significatif sur la viabilité dusystème destiné à être implanté.Cette thèse propose deux réflexions à propos de ces circuits d’acquisition. Une ces desréflexions a trait aux circuits d’amplification, à leur impédance d’entrée et à leurconsommation ; l’autre concerne un détecteur de potentiels d’action analogique, samodélisation et son optimisation.Ces travaux théoriques ayant abouti à des résultats concrets, un ASIC a été conçu,fabriqué, testé et caractérisé au cours de cette thèse. Cet ASIC à huit canaux comporte doncdes amplificateurs et des détecteurs de potentiels d’action analogiques et constitue le principalapport de ce travail de thèse. / Bioelectronics is a transdisciplinary field which develops interconnection devicesbetween biological systems presenting electrical activity and the world of electronics. Thiscommunication with living tissues implies to observe the electrical activity of the cells andtherefore requires an electronic acquisition chain.The use of Multi / Micro Electrode Array leads to systems that acquire a large numberof parallel channels, thus consumption and congestion of acquisition circuits have asignificant impact on the viability of the system to be implanted.This thesis proposes two reflections about these acquisition circuits. One of thesereflections relates to amplifier circuits, their input impedance and consumption; the otherconcerns an analogue action potentials detector, its modeling and optimization.These theoretical work leading to concrete results, an ASIC was designed,manufactured, tested and characterized in this thesis. This eight-channel ASIC thereforeincludes amplifiers and analogue action potentials detector and is the main contribution of thisthesis.

De nombreux dispositifs embarqués récents comme les téléphones portables, les GPS ou encore les consoles de jeu, possèdent un ou des haut-parleurs, chacun étant piloté par un amplificateur audio sur circuit intégré. De tels amplificateurs audio doivent répondre le mieux possible à quatre contraintes : une qualité audio satisfaisante, une immunité aux perturbations induites par le système, une faible consommation et une surface de silicium minimale. Ce travail de thèse sous contrat CIFRE a pour origine la création de l’entreprise Primachip en mai 2009 par Christian Dufaza et Hassan Ihs. Cette startup a été bâtie sur une architecture innovante d’amplificateur audio de classe D intégré. Son originalité repose sur le principe de rétroaction partielle qui s’applique à une boucle contenant un modulateur numérique Delta Sigma (ΔΣ) qui pilote l’étage de puissance et un convertisseur analogique-numérique (ADC) effectuant la rétroaction. Cela permet d’obtenir la stabilité de cette boucle tout en offrant une excellente réjection des bruits de l’étage de puissance. Un prototype sur silicium de l’architecture d’amplificateur de classe D numérique a été conçu et fabriqué. Un nouvel ADC ΔΣ temps continu a été développé pour ce prototype, afin d’obtenir des performances supérieures ou égales à l’état de l’art. Les résultats obtenus sur le circuit se sont révélés encourageants, bien que toutes les spécifications n’aient pas été atteintes. L’analyse des erreurs de ce premier circuit doit permettre la réalisation d’un amplificateur intégré exploitant au mieux cette architecture de classe D numérique. / Most current embedded devices, such as smartphones, GPS or portable consoles, feature one speaker or more, those speakers being driven by an integrated audio amplifier. This type of amplifier must meet four specifications: an adequate audio quality, to be immune to system disturbances, low power consumption and the smallest silicon area. This work takes its origin from the creation of Primachip in May 2009 by Christian Dufaza and Hassan Ihs. The aim of this startup was to develop and sell an innovative audio class-D amplifier for mobile market: the digital class-D concept. A partnership with the IM2NP laboratory was decided to propose a PhD topic under CIFRE contract (PhD in an industrial environment), in order to study and improve the amplifier architecture. Its originality is in the partial feedback concept which applies to a loop made of a digital ΔΣ modulator driving the power stage, with an analogue-to-digital converter (ADC) in the feedback path. It makes it possible to achieve stability while offering an outstanding power supply rejection. An integrated prototype of the class-D amplifier was designed, fabricated and evaluated. A new continuous-time ΔΣ ADC has been added to enable the digital class-D loop to achieve performances superior or equal to state of the art. The circuit measurement results were encouraging, although not ideal. The analysis of the prototype errors was performed. The conclusions should allow the design of an integrated audio amplifier making the best of the digital class-D architecture.

This dissertation thesis deals with design of new functional blocks usable in area of analogue signal processing, focusing on sensor signal processing. Versatility of these circuits will find applications in programmable analogue array structures that will be possible to control and configure via a digital signal. Hereby build-up array would be fully a reconfigurable digital control system for sensor signal processing and usable for a wide range of different sensors. It offers possibility to build-up a control code for each specific sensor system, with which it would be possible to achieve optimal results of the entire system and consequently place the system on a chip. The presented programmable array is designed from configurable analogue blocks. The current feedback circuits, which in a suitable configuration can operate in voltage or current mode, are used here. This allows to achieve very good results in the systems with very low power supply, which is closely associated with mobility and autonomous behavioral (that are very important and observed parameters today) of the entire sensor-based framework. The work deals in detail with particular blocks, which are described theoretically and evaluated for using in the programmable analogue array. Design of the structure of programmable analogue array as well the use of these circuits in the part of whole system (that will be realized on a chip) are presented at the end of this thesis.

This thesis presents the design of a mixed-signal CMOS multiplier implemented with short-channel PMOS transistors. The multiplier presented here forms the product of a differential input voltage and a five-bit digital code. A TSMC 0.18 µm MOSFET model is used to simulate the circuit in Cadence Design Systems. The research presented in this thesis reveals a configuration that allows the multiplier to run at a speed of 8.2 GHz with end-point nonlinearity less than 5%. The high speed and low nonlinearity make this circuit ideal for applications such as filtering and digital to analog conversion.

The rapid development in the semiconductors industry has enabled the placement of multiple chips on a single die. This has helped boost the functionality of modernday application specific integrated circuits (ASICs). Thus, digital circuits are being increasingly placed along-side analog and RF circuits in what are known as mixed signal circuits. As a result, the noise couplings through the substrate now have an increased role in mixed-signal ASIC design. Therefore, there is a need to study the effects of substrate noise and include them in the traditional design methodology. ∆Σ analog-to-digital converters (ADCs) are a perfect example of digital integration in traditionally analog circuits. ADCs, used to interface digital circuits to an analog world, are indispensable in mixed-signal systems and therefore set an interesting case study. A ∆Σ ADC is used in this thesis to study the effects of substrate noise. A background study is presented in the thesis to better understand ∆Σ modulators and substrate couplings. An intensive theoretical background on generation, propagation and reception of substrate noise is presented in light of existing researches. System and behavioural level models are proposed to include the effects of substrate noise in the design stages. A maximum decay of 10dB is seen due to injection of substrate noise system level simulations while a decay of 12dB is seen in behavioural simulations. A solution is proposed using controlled clock tree delays to overcome the effects of substrate noise. The solution is verified on both the system and behavioural levels. The noise models used to drive the studies can further be used in mixed-signal systems to design custom solutions. / Den snabba utvecklingen inom halvledarindustrin har möjliggjort placering av flera marker på en enda dö. Detta har hjälpt till att öka funktionaliteten hos moderna applikationsspecifika integrerade kretsar. Sålunda placeras digitala kretsar i allt högre grad parallella och RF-kretsar i de så kallade blandade signalkretsarna. Som ett resultat har bullerkopplingarna genom substratet nu en ökad roll i ASICdesign med blandad signal. Därför finns det behov av att studera effekterna av substratbuller och inkludera dem i den traditionella designmetoden. ∆Σ analog-till-digital omvandlare är ett perfekt exempel på digital integration i traditionellt analoga kretsar. ADC, som används för att gränssnitta digitala kretsar till en analog värld, är oumbärliga i blandningssignalsystem och är därför en intressant fallstudie. A ∆Σ arkitektur används i denna avhandling för att studera effekterna av substratstörning. En bakgrundsstudie presenteras i avhandlingen för att bättre förstå ∆Σ modulatorer och substratkopplingar. En intensiv teoretisk bakgrund på generering, förökning och mottagande av substratbuller presenteras i ljuset av befintliga undersökningar. Systemoch beteendemodellmodeller föreslås inkludera effekterna av substratbuller i konstruktionsstadiet. Ett maximalt förfall på 10dB ses på grund av injektion av substratbuller på systemnivå medan ett förfall av 12dB ses i beteende simuleringar.En lösning föreslås med hjälp av kontrollerade klockträdfördröjningar för att övervinna effekterna av substratbuller. Lösningen är verifierad på både system och beteendenivåer. De brusmodeller som används för att driva studierna kan vidare användas i blandningssignalsystem för att designa anpassade lösningar.

Many modern digital systems use forms of CMOS logical implementation due to the straight forward design nature of CMOS logic and minimal device area since CMOS uses fewer transistors than other logic families. To achieve high-performance requirements in mixed-signal chip development and quiet, noiseless circuitry, this thesis provides an alternative toCMOSin the form of MOS Current Mode Logic (MCML). MCML dissipates constant current and does not produce noise during value changing in a circuit CMOS circuits do. CMOS logical networks switch during clock ticks and with every device switching, noise is created on the supply and ground to deal with the transitions. Creating a noiseless standard cell library with MCML allows use of circuitry that uses low voltage switching with 1.5V between logic levels in a quiet or mixed-signal environment as opposed to the full rail to rail swinging of CMOS logic. This allows cohesive implementation with analog circuitry on the same chip due to constant current and lower switching ranges not creating rail noise during digital switching. Standard cells allow for the Cadence tools to automatically generate circuits and Cadence serves as the development platform for the MCML standard cells. The theory surrounding MCML is examined along with current and future applications well-suited for MCML are researched and explored with the goal of highlighting valid candidate circuits for MCML. Inverters and NAND gates with varying current drives are developed to meet these specialized goals and are simulated to prove viability for quiet, mixed-signal applications. Analysis and results show that MCML is a superior implementation choice compared toCMOSfor high speed and mixed signal applications due to frequency independent power dissipation and lack of generated noise during operation. Noise results show rail current deviations of 50nA to 300nA during switching over an average operating current of 20µA to 80µA respectively. The multiple order of magnitude difference between noise and signal allow the MCML cells to dissipate constant power and thus perform with no noise added to a system. Additional simulated results of a 31-stage ring oscillator result in a frequency for MCML of 1.57GHz simulated versus the 150.35MHz that MOSIS tested on a fabricated 31-stage CMOS oscillator. The layouts designed for the standard cell library conform to existing On Semiconductor ami06 technology dimensions and allow for design of any logical function to be fabricated. The I/O signals of each cell operate at the same input and output voltage swings which allow seamless integration with each other for implementation in any logical configuration.

The objective of this research is to develop and design front-end analog circuits for Capacitive Micromachined Ultrasound Transducers (CMUTs) and optical grating MEMS microphone. This work is motivated by the fact that with micro-scaling, MEMS sense capacitance gets smaller in a CMUT array element for intravascular ultrasound imaging, which has dimensions of 70um x 70um and sub pico-farad capacitance. Smaller sensors lead to a lower active-to-parasitic ratio and thus, degrads sensitivity. Area and power requirements are also very stringent, such as the case of intravascular catheter implementations with CMOS-First CMUT fabrication approach. In this implementation, capacitive feedback charge amplifier is an alternative approach to resistive feedback amplifiers. Capacitive feedback charge amplifier provides high sensitivity, small area, low distortion and saving power. This approach of charge amplifiers is also suitable in capacitive microphones where it provides low power and high sensitivity. Another approach to overcome capacitive detection challenges is to implement optical detection. In the case of biomimetic microphone structure, optical detection overcomes capacitive detection's thermal noise issues. Also with micro-scaling, optical detection overcomes the increased parasitics without any sensitivity degradation, unlike capacitive detection. For hearing aids, along with sensitivity, battery life is another challenge. We propose the use of 1-bit front-end sigma-delta ADC for overall improved hearing aid power efficiency. Front-end interface based on envelope detection and synchronous detection schemes have also been designed. These interface circuits consume currents in microampere range from a 1.5V battery. Circuit techniques are used for maximizing linear range and signal handling with low supplies. The entire front end signal processing with Vertical Cavity Surface Emitting Laser (VCSEL) drivers, photodiodes, filters and detectors is implemented on a single chip in 0.35um CMOS process.

<div>The huge gamut of today’s internet-connected embedded devices has led to increasing concerns regarding the security and confidentiality of data. To address these requirements, most embedded devices employ cryptographic algorithms, which are computationally secure. Despite such mathematical guarantees, as these algorithms are implemented on a physical platform, they leak critical information in the form of power consumption, electromagnetic (EM) radiation, timing, cache hits and misses, and so on, leading to side-channel analysis (SCA) attacks. Non-profiled SCA attacks like differential/correlational power/EM analysis (DPA/CPA/DEMA/CEMA) are direct attacks on a single device to extract the secret key of an encryption algorithm. On the other hand, profiled attacks comprise of building an offline template (model) using an identical device and the attack is performed on a similar device with much fewer traces.</div><div><br></div><div>This thesis focusses on developing efficient side-channel attacks and circuit-level low-overhead generic countermeasures. A cross-device deep learning-based profiling power side-channel attack (X-DeepSCA) is proposed which can break the secret key of an AES-128 encryption engine running on an Atmel microcontroller using just a single power trace, thereby increasing the threat surface of embedded devices significantly. Despite all these advancements, most works till date, both attacks as well as countermeasures, treat the crypto engine as a black box, and hence most protection techniques incur high power/area overheads.</div><div><br></div><div>This work presents the first white-box modeling of the EM leakage from a crypto hardware, leading to the understanding that the critical correlated current signature should not be passed through the higher metal layers. To achieve this goal, a signature attenuation hardware (SAH) is utilized, embedding the crypto core locally within the lower metal layers so that the critical correlated current signature is not passed through the higher metals, which behave as efficient antennas and its radiation can be picked up by a nearby attacker. Combination of the 2 techniques – current-domain signature suppression and local lower metal routing shows >350x signature attenuation in measurements on our fabricated 65nm test chip, leading to SCA resiliency beyond 1B encryptions, which is a 100x improvement in both EM and power SCA protection over the prior works with comparable overheads. Moreover, this is a generic countermeasure and can be utilized for any crypto core without any performance degradation.</div><div><br></div><div>Next, backed by our physics-level understanding of EM radiation, a digital library cell layout technique is proposed which shows >5x reduction in EM SCA leakage compared to the traditional digital logic gate layout design. Further, exploiting the magneto-quasistatic (MQS) regime of operation for the present-day CMOS circuits, a HFSS-based framework is proposed to develop a pre-silicon EM SCA evaluation technique to test the vulnerability of cryptographic implementations against such attacks during the design phase itself.</div><div><br></div><div>Finally, considering the continuous growth of wearable and implantable devices around a human body, this thesis also analyzes the security of the internet-of-body (IoB) and proposes electro-quasistatic human body communication (EQS-HBC) to form a covert body area network. While the traditional wireless body area network (WBAN) signals can be intercepted even at a distance of 5m, the EQS-HBC signals can be detected only up to 0.15m, which is practically in physical contact with the person. Thus, this pioneering work proposing EQS-HBC promises >30x improvement in private space compared to the traditional WBAN, enhancing physical security. In the long run, EQS-HBC can potentially enable several applications in the domain of connected healthcare, electroceuticals, augmented and virtual reality, and so on. In addition to these physical security guarantees, side-channel secure cryptographic algorithms can be augmented to develop a fully secure EQS-HBC node.</div>

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