No description available.

No description available.

No description available.

As Orthogonal Frequency Division Multiplexing (OFDM) becomes more prevalent in new leading-edge data rate systems processing spectral bandwidths beyond 1 GHz, the required operating speed of the baseband signal processing, specifically the Analog- to-Digital Converter (ADC) and Fast Fourier Transform (FFT) processor, presents significant circuit design challenges and consumes considerable power. Additionally, since Ultra-WideBand (UWB) systems operate in an increasingly crowded wireless environment at low power levels, the ability to tolerate large blocking signals is critical. The goals of this work are to reduce the disproportionately high power consumption found in UWB OFDM receivers while increasing the receiver linearity to better handle blockers. To achieve these goals, an alternate receiver architecture utilizing a new FFT processor is proposed. The new architecture reduces the volume of information passed through the ADC by moving the FFT processor from the digital signal processing (DSP) domain to the discrete time signal processing domain. Doing so offers a reduction in the required ADC bit resolution and increases the overall dynamic range of the UWB OFDM receiver. To explore design trade-offs for the new discrete time (DT) FFT processor, system simulations based on behavioral models of the key functions required for the processor are presented. A new behavioral model of the linear transconductor is introduced to better capture non-idealities and mismatches. The non-idealities of the linear transconductor, the largest contributor of distortion in the processor, are individually varied to determine their sensitivity upon the overall dynamic range of the DT FFT processor. Using these behavioral models, the proposed architecture is validated and guidelines for the circuit design of individual signal processing functions are presented. These results indicate that the DT FFT does not require a high degree of linearity from the linear transconductors or other signal processing functions used in its design. Based on the results of the system simulations, a prototype 8-point DT FFT processor is designed in 130 nm CMOS. The circuit design and layout of each of the circuit functions; serial-to-parallel converter, FFT signal flow graph, and clock generation circuitry is presented. Subsequently, measured results from the first proof-of-concept IC are presented. The measured results show that the architecture performs the FFT required for OFDM demodulation with increased linearity, dynamic range and blocker handling capability while simultaneously reducing overall receiver power consumption. The results demonstrate a dynamic range of 49 dB versus 36 dB for the equivalent all-digital signal processing approach. This improvement in dynamic range increases receiver performance by allowing detection of weak sub-channels attenuated by multipath. The measurements also demonstrate that the processor rejects large narrow-band blockers, while maintaining greater than 40 dB of dynamic range. The processor enables a 10x reduction in power consumption compared to the equivalent all digital processor, as it consumes only 25 mWatts and reduces the required ADC bit depth by four bits, enabling application in hand-held devices. Following the success of the first proof-of-concept IC, a second prototype is designed to incorporate additional functionality and further demonstrate the concept. The second proof-of-concept contains an improved version of the serial-to-parallel converter and clock generation circuitry with the additional function of an equalizer and parallel- to-serial converter. Based on the success of system level behavioral simulations, and improved power consumption and dynamic range measurements from the proof-of-concept IC, this work represents a contribution in the architectural development and circuit design of UWB OFDM receivers. Furthermore, because this work demonstrates the feasibility of discrete time signal processing techniques at 1 GSps, it serves as a foundation that can be used for reducing power consumption and improving performance in a variety of future RF/mixed-signal systems. / Ph. D.

The conventional approach to validate the analog and mixed signal designs utilizes extensive SPICE-level simulations. The main challenge in this approach is to know when all important corner cases have been simulated. An alternate approach is to use the formal verification techniques. Formal verification techniques have gained wide spread popularity in the digital design domain; but in case of analog and mixed signal designs, a large number of test scenarios need to be designed to generate sufficient simulation traces to test out all the specified system behaviours. Analog and mixed signal designs can be formally modeled as hybrid systems and therefore techniques used for formal analysis and verification of hybrid systems can be applied to the analog and mixed signal designs. Generally, formal verification tools for hybrid systems work at the abstract level where we model the systems in terms of differential equations or algebraic equations. However the analog and mixed signal system designers are very comfortable in designing the circuits at the transistor level. To bridge the gap between abstraction level verification and the designs validation which has been implemented at the transistor level, the very important issue we need to address is: Can we formally verify the circuits at the transistor level itself? For this we have proposed a framework for doing the formal verification of analog and mixed signal designs using SPICE simulation traces in one of the hybrid systems formal verification tools (i.e. Checkmate from CMU). An extension to a formal verification approach of hybrid systems is proposed to verify analog and mixed signal (AMS) designs. AMS designs can be formally modeled as hybrid systems and therefore lend themselves to the formal analysis and verification techniques applied to hybrid systems. The proposed approach employs simulation traces obtained from an actual design implementation of AMS circuit blocks (for example, in the form of SPICE netlists) to carry out formal analysis and verification. This enables the same platform used for formally validating an abstract model of an AMS design to be also used for validating its different refinements and design implementation, thereby providing a simple route to formal verification at different levels of implementation. Our approach has been illustrated through the case studies using simulation traces form the different frameworks i.e. Simulink/Stateflow framework and the SPICE simulation traces. We demonstrate the feasibility of our approach around the Checkmate and the case studies for hybrid systems and the analog and mixed signal designs.

Recent ULSI (ultra large scale integration) technology emphasizes small size devices, featuring low power and high switching speed. Moore's law has been followed<br>successfully in scaling down the silicon device in order to enhance the level of integration with high performances until conventional devices failed to cop up with further scaling due to limitations with ballistic effects, and challenges with accommodating dopant fluctuation, mobility degradation, among other device parameters. Recently, Graphene based devices offered alternative approach, featuring small size<br>and high performances. This includes high carrier mobility, high carrier density, high robustness, and high thermal conductivity. These unique characteristics made the<br>Graphene devices attractive for high speed electronic architectures. In this research, Graphene devices were integrated into applications with analog, digital, and mixed<br>signals based systems.<br>Graphene devices were briefly explored in electronics applications since its first model developed by the University of Illinois, Champaign in 2013. This study emphasizes the validation of the model in various applications with analog, digital, and mixed signals. At the analog level, the model was used for voltage and power amplifiers; classes A, B, and AB. At the digital level, the device model was validated within the universal gates, adders, multipliers, subtractors, multiplexers, demultiplexers, encoders, and comparators. The study was also extended to include Graphene devices<br><div>for serializers, the digital systems incorporated into the data structure storage. At the mixed signal level, the device model was validated for the DACs/ADCs. In all components, the features of the new devices were emphasized as compared with the existing silicon technology. The system functionality and dynamic performances were also elaborated. The study also covered the linearity characteristics of the devices within full input range operation.</div><div>GNRFETs with a minimum channel length of 10nm and an input voltage 0.7V were considered in the study. An electronic design platform ADS (Advanced Design<br>Systems) was used in the simulations. The power amplifiers showed noise figure as low as 0.064dbs for class A, and 0.32 dbs for class B, and 0.69 dbs for class AB power<br>amplifiers. The design was stable and as high as 5.12 for class A, 1.02 for class B, and 1.014 for class AB. The stability factor was estimated at 2GHz operation. The harmonics were as low as -100 dbs for class A, -60 dbs for class B, and -50dbs for class AB, all simulated at 1GHz. The device was incorporated into ADC system, and as<br>low as 24.5 micro Watt power consumption and 40 nsec rise time were observed. Likewise, the DAC showed low power consumption as of 4.51 micro Watt. The serializer showed as minimum power consumption of the order of 0.4mW. <br></div><div>These results showed that these nanoscale devices have potential future for high-speed communication systems, medical devices, computer architecture and dynamic<br>Nano electromechanical (NEMS) which provides ultra-level of integration, incorporating embedded and IoT devices supporting this technology. Results of analog and<br>digital components showed superiority over other silicon transistor technologies in their ultra-low power consumption and high switching speed.<br></div><div><br></div>

This work investigates energy-efficient approximate computation for solving differential equations. It extends the analog computing techniques to a new paradigm: continuous-time hybrid computation, where both analog and digital circuits operate in continuous time. In this approach, the time intervals in the digital signals contain important information. Unlike conventional synchronous digital circuits, continuous-time digital signals offer the benefits of adaptive power dissipation and no quantization noise. Two prototype chips have been fabricated in 65 nm CMOS technology and tested successfully. The first chip is capable of solving nonlinear differential equations up to 4th order, and the second chip scales up to 16th order based on the first chip. Nonlinear functions are generated by a programmable, clockless, continuous-time 8-bit hybrid architecture (ADC+SRAM+DAC). Digitally-assisted calibration is used in all analog/mixed-signal blocks. Compared to the prior art, our chips makes possible arbitrary nonlinearities and achieves 16 times lower power dissipation, thanks to technology scaling and extensive use of class-AB analog blocks. Typically, the unit achieves a computational accuracy of about 0.5% to 5% RMS, solution times from a fraction of 1 micro second to several hundred micro seconds, and total computational energy from a fraction of 1 nJ to hundreds of nJ, depending on equation details. Very significant advantages are observed in computational speed and energy (over two orders of magnitude and over one order of magnitude, respectively) compared to those obtained with a modern MSP430 microcontroller for the same RMS error.

With increased and varied performance demands, it is essential that complex multi-standard radio/systems coexist on a same chip. To have cost and performance benefits, these analog/RF systems are implemented in scaled nanometer nodes. At these nodes, the high level of variability in process variations is making the task of manufacturing high fidelity systems a challenge leading to yield and reliability issues. Hence, in the post-manufacturing phase, test and diagnosis steps are critical to identify the cause and effect of the process variations. Further, intelligent post-manufacturing tuning techniques are required to correct the effect of process variations on analog/RF systems. In this work, a die-level concurrent test and diagnosis approach using optimized measurements obtained in high volume manufacturing environment is proposed for analog/RF circuits. Such a simultaneous test and diagnosis methodology enables monitoring parametric process shifts and providing rapid feedback to the fab to minimize or prevent yield loss. In the case of devices that are continuously operating in the field, an efficient on-line diagnosis approach has been developed to perform reliability related prognosis. For advanced RF technologies such as MIMO-OFDM systems, a rapid system-level testing scheme is presented that performs concurrent testing of the multiple RF chains. Depending on the availability of the computational resources and system tuning knobs, different low-cost methodologies for post-manufacture tuning or self-healing of RF SISO/MIMO systems are developed. These include faster digital monitoring and tuning techniques, on-chip tuning techniques using digital logic that enables die-level self-tuning, and DSP-based power conscious iterative techniques for SISO/MIMO RF systems. An adaptive power-performance tuning technique is developed for those devices that have a post-manufacture power consumption value that is more than the acceptable limit. These intelligent post-manufacturing techniques result in reduced manufacturing cost, improved yield, and reliability of analog/RF systems.

The integration of mixed-signal systems has long been a problem in the semiconductor industry. CMOS System-on-Chip (SOC), the traditional means for integration, fails mixed-signal systems on two fronts; the lack of on-chip passives with high quality (Q) factors inhibits the design of completely integrated wireless circuits, and the noise coupling from digital to analog circuitry through the conductive silicon substrate degrades the performance of the analog circuits. Advancements in semiconductor packaging have resulted in a second option for integration, the System-On-Package (SOP) approach. Unlike SOC where the package exists just for the thermal and mechanical protection of the ICs, SOP provides for an increase in the functionality of the IC package by supporting multiple chips and embedded passives. However, integration at the package level also comes with its set of hurdles, with significant research required in areas like design of circuits using embedded passives and isolation of noise between analog and digital sub-systems. A novel multiband balun topology has been developed, providing concurrent operation at multiple frequency bands. The design of compact wideband baluns has been proposed as an extension of this theory. As proof-of-concept devices, both singleband and wideband baluns have been fabricated on Liquid Crystalline Polymer (LCP) based organic substrates. A novel passive-Q based optimization methodology has been developed for chip-package co-design of CMOS Low Noise Amplifiers (LNA). To implement these LNAs in a mixed-signal environment, a novel Electromagnetic Band Gap (EBG) based isolation scheme has also been employed. The key contributions of this work are thus the development of novel RF circuit topologies utilizing embedded passives, and an advancement in the understanding and suppression of signal coupling mechanisms in mixed-signal SOP-based systems. The former will result in compact and highly integrated solutions for RF front-ends, while the latter is expected to have a significant impact in the integration of these communication devices with high performance computing.

The proliferation of wireless communication devices in the recent past has increased the pressure on semiconductor manufacturers to produce quality radio frequency (RF) modules and systems at a low cost. This entails reducing their test cost as well, since the cost of testing modern RF devices can be up to 40% of their manufacturing cost. The high test cost of these devices can be mainly attributed to (a) the expensive nature of the RF automated test equipment (ATE) used to perform wafer-level and fully packaged RF functionality tests, (b) limited test point access for the application and capture of test signals, (c) the long test development and application times, and (d) the lack of diagnostic tools to evaluate and improve the performance of loadboards and test resources in high-volume tests. In this thesis, a framework for the efficient production testing of high-performance RF modules and systems using low-cost ATE is presented. This framework uses low-speed, low-resolution test resources to generate reliable tests for complex RF systems. Also, the test resources will be evaluated and improved ahead of high-volume tests to improve test yield and throughput. The components of the proposed framework are: (1) Genetic ATPG for reliable test stimulus generation using low-resolution test resources: A genetic algorithm (GA) based automatic test pattern generator (ATPG) to optimize the alternate test stimulus for reliable testing of complex RF systems using low-resolution, low-cost test resources. These test resources may be on-chip or off-chip. (2) Concurrent voltage/current alternate test methodology: A testing framework for efficiently testing the high-frequency specifications of RF systems using low-frequency spectral and/or transient current signatures. Suitable on-chip and/or off-chip design-for-test (DfT) resources are used to enable the source and capture operations at lower frequencies. (3) Loadboard checker: A checker tool to accurately characterize/diagnose the DfT resources on the RF loadboards used to enable test of RF devices/systems using low-cost ATE. (4) Advanced test signal processing algorithms: The performance of the low-cost ATE resources, in terms of their linearity/resolution, will be evaluated and improved to enable the accurate capture of the test response signals.