A multi band orthogonal frequency division multiplexing (MB-OFDM) compatible ultra wideband (UWB) receiver with narrowband interference (NBI) suppression capability is presented. The average transmit power of UWB system is limited to -41.3 dBm/MHz in order to not interfere existing narrowband systems. Moreover, it must operate even in the presence of unintentional radiation of FCC Class-B compatible devices. If this unintentional radiation resides in the UWB band, it can jam the communication. Since removing the interference in digital domain requires higher dynamic range of analog front-end than removing it in analog domain, a programmable analog notch filter is used to relax the receiver requirements in the presence of NBI. The baseband filter is placed before the variable gain amplifier (VGA) in order to reduce the signal swing at the VGA input. The frequency hopping period of MB-OFDM puts a lower limit on the settling time of the filter, which is inverse proportional to notch bandwidth. However, notch bandwidth should be low enough not to attenuate the adjacent OFDM tones. Since these requirements are contradictory, optimization is needed to maximize overall performance. Two different NBI suppression schemes are tested. In the first scheme, the notch filter is operating for all sub-bands. In the second scheme, the notch filter is turned on during the sub-band affected by NBI. Simulation results indicate that the UWB system with the first and the second suppression schemes can handle up to 6 dB and 14 dB more NBI power, respectively. The results of this work are not limited to MB-OFDM UWB system, and can be applied to other frequency hopping systems.

En esta tesis doctoral se plantea la mejora de la capacidad de transmisión en las redes HDR-WPAN ( redes WPAN con elevada tasa binaria) empleando el estándar MB-OFDM (OFDM sobre múltiples bandas) en canales UWB con modulación adaptativa realizando una adaptación discreta de la tasa de bits transmitidos por subportadora. La tesis comienza con un análisis en el dominio del tiempo y de la frecuencia de los dos modelos de canal UWB propuestos en IEEE: IEEE 802.15.3a y 802.15.4a. El objetivo consiste en determinar la distribución estadística que mejor se aproxima a la amplitud de cada una de las subportadoras, para posteriormente definir la métrica a emplear en la evaluación del estado y dinámica del canal UWB. En la modulación adaptativa se requiere que el transmisor se adapte a la variabilidad del canal. El análisis se puede realizar de dos formas: - Asumiendo adaptación perfecta (estimación ideal), lo que implica que el transmisor siempre conoce la dinámica y estructura del canal. - Considerando un error (estimación imperfecta del canal) en la adaptación debido a la incertidumbre en el conocimiento del canal. El método de estimación del canal UWB empleado en la tesis se fundamenta en el conocimiento del coeficiente de correlación en potencia entre las subportadoras de datos y la subportadora piloto. A partir de la información sobre el estado del canal, u una vez definida la métrica que permite su evaluación, se calculan las prestaciones de la modulación adaptativa. Esta evaluación se realiza a través de expresiones cerradas para la capacidad media, la probabilidad de error de bit media y la probabilidad de bloqueo, así como la obtención de la distribución y estadísticos del error de estimación en el caso de estimación imperfecta del canal. Por otro lado, a partir de la distribución estadística de la amplitud de cada una de las subportadoras en frecuencia del canal UWB, se obtienen resultados respecto a la variación de potencia del canal en función del ancho de banda . / Llano Ramírez, G. (2010). Modelado en frecuencia del canal UWB y su aplicación en el análisis de técnicas de modulación adaptativa en sistemas MB-OFDM UWB para redes WPAN [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/8429 / Palancia

Aujourd'hui, le format « Quadrature Phase Shift Keying » avec multiplexage de polarisation (DP-QPSK) opérant à 100 Gbps est devenue un standard pour la transmission WDM longue distance. Une alternative au format DP-QPSK permettant d’atteindre des débits de 100 Gbps et plus (400 G & 1Tbps) est l’ « Orthogonal Frequency Division Multiplexing » (OFDM). Mais, des interrogations subsistent quant à sa robustesse aux effets non linéaires. Dans cette thèse nous avons étudié le potentiel de la technologie OFDM pour la transmission WDM longue distance à 100 Gbps. Le traitement du signal est détaillé ainsi que la mise en œuvre du transmetteur et récepteur OFDM cohérent. Nous présentons aussi les résultats expérimentaux de la transmission obtenus dans plusieurs configurations. Dans l’une de ces configurations, le canal modulé avec le format DP-OFDM coherent (Co-DP-OFDM) est multiplexé avec 40 canaux modulés en DP-QPSK à 100 Gbps. Les canaux ont ensuite été transmis sur 1000 km de fibre G.652 sans gestion de dispersion chromatique. Dans une autre configuration, les canaux Co-DP-OFDM et Co-DP-QPSK sont combinés avec 78 canaux 10 Gbps NRZ-OOK et transmis sur 1000 km de fibre G.652 avec gestion de dispersion. Nous avons montré que le Co-DP-OFDM et Co-DP-QPSK ont des performances similaires après une transmission de 1000 km sur une ligne sans gestion de dispersion, et nous avons aussi montré que la transmission de ces formats sur une infrastructure de fibre deployée est possible à condition de réduire de 5 dB la puissance des canaux 10 Gbps NRZ-OOK par rapport aux canaux à100 Gbps. Ces résultats sont précieux pour la prochaine génération de systèmes WDM à 400 Gbps ou 1 Tbps. / Today the 100 Gbps coherent dual polarization quadrature phase shift keying (Co-DP-QPSK) is standardized as the industrial solution for long-haul WDM transmission. Another alternative format to DP-QPSK that permits also to reach a data rate of 100 Gbps and beyond is the coherent orthogonal frequency division multiplexing (OFDM) format. However a doubt exists over the ability of OFDM to be as efficient as QPSK for long-haul WDM transmission due to its supposed higher sensitivity to nonlinear effects . In this thesis, we have investigated the potential of Co-DP-OFDM for 100 Gbps WDM transport. The digital signal processing algorithms are detailed as well as the various experimental set-ups required to carry out and validate the 100 Gbps transceiver. We also present the transmission results obtained with several configurations. In one of these configurations, the 100 Gbps Co-DP-OFDM channel is multiplexed with forty 100 Gbps DP-QPSK channels and all these channels are transmitted over 1000 km of DCF-free G.652 fiber, while in another configuration, the Co-DP-OFDM and Co-DP-QPSK channels are combined with seventy eight 10 Gbps NRZ-OOK channels and transmitted over 1000 km of dispersion managed G.652 fiber line. We have demonstrated that OFDM and QPSK have nearly the same performance after a transmission over 1000 km, and also we have demonstrated that the transmission of these two formats over legacy fiber infrastructure is possible under the condition of decreasing by 5 dB the 10 Gbps NRZ-OOK channel power with respect to the 100 Gbps channels. The results presented in this thesis are very valuable when considering the next generation of 400 Gbps or 1 Tbps for WDM systems.

Lors du développement d’un nouvel avion, la phase précédant l’obtention du certificat de navigabilité est basée sur de nombreux essais au sol ou en vol. Dans le domaine spatial, le lancement est l’une des phases les plus critiques pour les systèmes et des essais au sol particulièrement rigoureux sont donc réalisés afin de vérifier que la charge utile ne sera pas endommagéeDes milliers de capteurs de pression ou de jauges de contrainte sont ainsi utilisés par les industriels du secteur pour ce type d’essais. Mais tous ces éléments sont aujourd’hui connectés par des fils, ce qui engendre des contraintes de temps, de coût et de limitation du nombre de capteurs. Leur remplacement par des réseaux de capteurs sans fil est une solution évidente qui permet également d’augmenter le nombre de points de mesure. Cependant, il n’existe aujourd’hui aucun protocole permettant de répondre aux attentes et besoins des professionnels de l’aéronautique et du spatial. Les travaux présentés dans cette thèse ont ainsi vocation à répondre aux besoins d’un canal de communication très haut débit, basse consommation, à faible puissance d’émission, fiable et autorisant un grand nombre de nœuds. Un prototype de couche physique basée sur un système OFDM ultra large bande a été réalisé, testé et validé, et permet d’atteindre un débit de plus de 200 Mbits/s. / To evaluate a system's compliance with its specified requirements, Hardware System Testing is conducted on the complete and integrated system. This phase is essential in all industry branches, especially in the very regulated and critical aerospace world. In the final phase of the development of an airplane, flight test equipment gathers and analyzes data during flight to evaluate the flight characteristics of the aircraft and validate its design, including safety aspects. One of the most critical tests is the measure of the pressure around the wings during flight. All new aircrafts are computer designed with the use of virtual wind tunnels. So very accurate measures have to be done on the aircraft to validate the model before the aircraft can be industrially produced. In the case of satellites, vibration and mechanical stress are two critical phenomena a satellite endures during launch. This is leading to the necessity for accurate ground tests using strain gauges or thermal sensors before allowing a launch. All such systems used by aircraft and satellite manufacturers today are wired systems. Sensors put around the wings or inside the satellite compartments are wired to a concentrator inside the cabin or the operator’s room. Although good performances are observed in terms of measurement accuracy, these systems have strong drawbacks. The two most important ones are the weight and the cost of both the systems and their installation. An additional drawback concerning its use on aircrafts is due to the installation of a system that increases the weight of the aircraft and immobilizes it during many weeks due to the routing of every cable inside the wings. The cost and the complexity of such systems don’t allow a great number of measurement points. The replacement of conventional measurement networks by wireless sensor networks is not an obvious solution. Despite the great interest in wireless sensor networks in the recent years, the technological barriers are still very numerous and there is currently no protocol to meet the expectations and needs of aviation professionals. The work presented in this thesis aims to meet the needs of a high-speed, low power consumption, low emission and reliable communication layer. Measurements have been performed in real conditions using commercial devices based on the protocol MB-OFDM/Wimedia, the most common standard that approach the need expressed, and have served to define the basis of the study and have helped to select best development tracks. Measurements have demonstrated also the specificity of the propagation channel. In order to reduce the time between the choice of algorithms and their testing in real conditions, it became necessary to use a design flow called Specification - Exploration – Improvement based on automatic synthesis tools. This development cycle has identified specific material needs for the design of the demonstrator.The physical layer is based on an OFDM system and UWB to achieve a data rate of over 150 Mb/s. A fully functional demonstrator, implemented on FPGA and composed of four communicating nodes was presented and has been used to validate the physical layer. Finally first steps to develop a digital ASIC are presented to achieve the goal of low power consumption

The allocation of frequency spectrum by the FCC for Ultra Wideband (UWB) communications in the 3.1-10.6 GHz has paved the path for very high data rate Gb/s wireless communications. Frequency synthesis in these communication systems involves great challenges such as high frequency and wideband operation in addition to stringent requirements on frequency hopping time and coexistence with other wireless standards. This research proposes frequency generation schemes for such radio systems and their integrated implementations in silicon based technologies. Special emphasis is placed on efficient frequency planning and other system level considerations for building compact and practical systems for carrier frequency generation in an integrated UWB radio. This work proposes a frequency band plan for multiband OFDM based UWB radios in the 3.1-10.6 GHz range. Based on this frequency plan, two 11-band frequency synthesizers are designed, implemented and tested making them one of the first frequency synthesizers for UWB covering 78% of the licensed spectrum. The circuits are implemented in 0.25µm SiGe BiCMOS and the architectures are based on a single VCO at a fixed frequency followed by an array of dividers, multiplexers and single sideband (SSB) mixers to generate the 11 required bands in quadrature with fast hopping in much less than 9.5 ns. One of the synthesizers is integrated and tested as part of a 3-10 GHz packaged receiver. It draws 80 mA current from a 2.5 V supply and occupies an area of 2.25 mm2. Finally, an architecture for a UWB synthesizer is proposed that is based on a single multiband quadrature VCO, a programmable integer divider with 50% duty cycle and a single sideband mixer. A frequency band plan is proposed that greatly relaxes the tuning range requirement of the multiband VCO and leads to a very digitally intensive architecture for wideband frequency synthesis suitable for implementation in deep submicron CMOS processes. A design in 130nm CMOS occupies less than 1 mm2 while consuming 90 mW. This architecture provides an efficient solution in terms of area and power consumption with very low complexity.

The aim of the Master’s Thesis is to describe ideas of the MB-OFDM principle that represents the possibility of OFDM principle implementation in ultra wideband systems. There are compared physical layers of the IEEE 802.15.3a and the ECMA-368 standard which include the MB-OFDM principle. In practical part of the thesis, there was created a model of ECMA-368 physical layer in MATLAB environment including CDMA access principle. Finally, the MB OFDM system resistance against disturbance and the Peak-to-Average-Power Ratio is analyzed and commented.

A high-throughput low-power Soft-Output Viterbi decoder designed for the convolutional codes used in the ECMA-368 UWB standard is presented in this thesis. The ultra wide band (UWB) wireless communication technology is supposed to be used in physical layer of the wireless personal area network (WPAN) and next generation Blue Tooth. MB-OFDM is a very popular scheme to implement the UWB system and is adopted as the ECMA-368 standard. To make the high speed data transferred over the channel reappear reliably at the receiver, the error correcting codes (ECC) are wildly utilized in modern communication systems. The ECMA-368 standard uses concatenated convolutional codes and Reed-Solomon (RS) codes to encode the PLCP header and only convolutional codes to encode the PPDU Payload. The Viterbi algorithm (VA) is a popular method of decoding convolutional codes for its fairly low hardware implementation complexity and relatively good performance. Soft-Output Viterbi Algorithm (SOVA) proposed by J. Hagenauer in 1989 is a modified Viterbi Algorithm. A SOVA decoder can not only take in soft quantized samples but also provide soft outputs by estimating the reliability of the individual symbol decisions. These reliabilities can be provided to the subsequent decoder to improve the decoding performance of the concatenated decoder. The SOVA decoder is designed to decode the convolutional codes defined in the ECMA-368 standard. Its code rate and constraint length is R=1/3 and K=7 respectively. Additional code rates derived from the "mother" rate R=1/3 codes by employing "puncturing", including 1/2, 3/4, 5/8, can also be decoded. To speed up the add-compare-select unit (ACSU), which is always the speed bottleneck of the decoder, the modified CSA structure proposed by E.Yeo is adopted to replace the conventional ACS structure. Besides, the seven-level quantization instead of the traditional eight-level quantization is proposed to be used is in this decoder to speed up the ACSU in further and reduce its hardware implementation overhead. In the SOVA decoder, the delay line storing the path metric difference of every state contains the major portion of the overall required memory. A novel hybrid survivor path management architecture using the modified trace-forward method is proposed. It can reduce the overall required memory and achieve high throughput without consuming much power. In this thesis, we also give the way to optimize the other modules of the SOVA decoder. For example, the first K-1 necessary stages in the Path Comparison Unit (PCU) and Reliability Measurement Unit (RMU) are IX removed without affecting the decoding results. The attractiveness of SOVA decoder enables us to find a way to deliver its soft output to the RS decoder. We have to convert bit reliability into symbol reliability because the soft output of SOVA decoder is the bit-oriented while the reliability per byte is required by the RS decoder. But no optimum transformation strategy exists because the SOVA output is correlated. This thesis compare two kinds of the sub-optimum transformation strategy and proposes an easy to implement scheme to concatenate the SOVA decoder and RS decoder under various kinds of convolutional code rates. Simulation results show that, using this scheme, the concatenated SOVA-RS decoder can achieve about 0.35dB decoding performance gain compared to the conventional Viterbi-RS decoder.

As Orthogonal Frequency Division Multiplexing (OFDM) becomes more prevalent in new leading-edge data rate systems processing spectral bandwidths beyond 1 GHz, the required operating speed of the baseband signal processing, specifically the Analog- to-Digital Converter (ADC) and Fast Fourier Transform (FFT) processor, presents significant circuit design challenges and consumes considerable power. Additionally, since Ultra-WideBand (UWB) systems operate in an increasingly crowded wireless environment at low power levels, the ability to tolerate large blocking signals is critical. The goals of this work are to reduce the disproportionately high power consumption found in UWB OFDM receivers while increasing the receiver linearity to better handle blockers. To achieve these goals, an alternate receiver architecture utilizing a new FFT processor is proposed. The new architecture reduces the volume of information passed through the ADC by moving the FFT processor from the digital signal processing (DSP) domain to the discrete time signal processing domain. Doing so offers a reduction in the required ADC bit resolution and increases the overall dynamic range of the UWB OFDM receiver. To explore design trade-offs for the new discrete time (DT) FFT processor, system simulations based on behavioral models of the key functions required for the processor are presented. A new behavioral model of the linear transconductor is introduced to better capture non-idealities and mismatches. The non-idealities of the linear transconductor, the largest contributor of distortion in the processor, are individually varied to determine their sensitivity upon the overall dynamic range of the DT FFT processor. Using these behavioral models, the proposed architecture is validated and guidelines for the circuit design of individual signal processing functions are presented. These results indicate that the DT FFT does not require a high degree of linearity from the linear transconductors or other signal processing functions used in its design. Based on the results of the system simulations, a prototype 8-point DT FFT processor is designed in 130 nm CMOS. The circuit design and layout of each of the circuit functions; serial-to-parallel converter, FFT signal flow graph, and clock generation circuitry is presented. Subsequently, measured results from the first proof-of-concept IC are presented. The measured results show that the architecture performs the FFT required for OFDM demodulation with increased linearity, dynamic range and blocker handling capability while simultaneously reducing overall receiver power consumption. The results demonstrate a dynamic range of 49 dB versus 36 dB for the equivalent all-digital signal processing approach. This improvement in dynamic range increases receiver performance by allowing detection of weak sub-channels attenuated by multipath. The measurements also demonstrate that the processor rejects large narrow-band blockers, while maintaining greater than 40 dB of dynamic range. The processor enables a 10x reduction in power consumption compared to the equivalent all digital processor, as it consumes only 25 mWatts and reduces the required ADC bit depth by four bits, enabling application in hand-held devices. Following the success of the first proof-of-concept IC, a second prototype is designed to incorporate additional functionality and further demonstrate the concept. The second proof-of-concept contains an improved version of the serial-to-parallel converter and clock generation circuitry with the additional function of an equalizer and parallel- to-serial converter. Based on the success of system level behavioral simulations, and improved power consumption and dynamic range measurements from the proof-of-concept IC, this work represents a contribution in the architectural development and circuit design of UWB OFDM receivers. Furthermore, because this work demonstrates the feasibility of discrete time signal processing techniques at 1 GSps, it serves as a foundation that can be used for reducing power consumption and improving performance in a variety of future RF/mixed-signal systems. / Ph. D.

Ever since the FCC allocated 7.5 GHz (from 3.1 GHz to 10.6 GHz) for ultra wideband (UWB) technology, interest has been renewed in both academic and industrial circles to exploit this vast spectrum for short range, high data rate wireless applications. The great potential of UWB lies in the fact that it can co-exist with the already licensed spectrum users and can still pave the way for a wide range of applications. However, this wide bandwidth complicates the circuit level implementation of key RF blocks like the power amplifier (PA), transmit/receive switch, low noise amplifier (LNA) and mixers in an UWB transceiver. Though expensive technologies like SiGe or GaAs have been used for transceiver realizations, the ultimate goal is to have a single-chip, low-cost solution which can only be achieved by using CMOS technology. Nevertheless, some of the inherent limitations of CMOS like lower fT of transistors make the design of UWB circuits in CMOS an extremely challenging task. Two proposals- Multi-Band OFDM and Direct-Sequence CDMA have been put before the IEEE 802.15.3a task group to decide on the industry standard for the commercial deployment of this technology. Though the debate on which standard is better has not been resolved, proponents of both the groups have already begun to develop prototypes of their respective proposals. This thesis describes the design of a key RF block in the UWB transceiver - the Power Amplifier. For the first part of this work, a PA suitable for MB-OFDM specifications was designed and fabricated in TSMC 0.18um CMOS technology. The class-AB PA is able to cover the lower UWB frequency band from 3.1 GHz to 4.75 GHz and delivers an output power of -2 dBm at 4 GHz. Simulated results show a gain of 19±2 dB achieved over the entire band and the PA consumes 36.54 mW from a 1.8V supply. In the second part of this work, a PA that meets the DS-CDMA specifications was designed and fabricated. This PA operates in the class-AB regime, delivering an output power of -4.2 dBm with input-1dB compression point at -22 dBm. Complete design and implementation was done using TSMC 0.18um CMOS technology and it consumes a very low power of 25 mW, while realizing a flat gain of 19±1 dB across the whole band of operation. All the above mentioned results are from simulations in SpectreRF and measurements are yet to be taken. Additional features like power ON/OFF scheme and output impedance control has also been incorporated in the design. / Master of Science

The advent of software radio technology has enabled radio developers to design and implement radios with great ease and flexibility. Software radios are effective in experimentation and development of radio designs. However, they have limitations when it comes to high-speed, high-throughput designs. This limitation can be overcome by introducing a hardware element to the software radio platform. Enhancing GNU Radio for Hardware Accelerated Radio Design project implements such a scheme by augmenting an FPGA co-processor to a conventional GNU Radio flow. In this thesis, this novel platform is evaluated in terms of performance of a radio design, as well as hardware and software system requirements. A simple and efficient Zigbee receiver design is presented. Implementation of this receiver is used as a proof-of-concept for the effectiveness and design methodology of the modified GNU Radio. This work also proposes a scheme to extend this idea for design of ultra-wideband radio systems based on multiband-OFDM. / Master of Science