The rapid growth of communication technology with the success of internet, has brought huge profits and great convenience to our daily life. Computer networks can be built using either wired or wireless technologies. It will be an important issue that how to select a medium for the transmission. Wired Ethernet has been the traditional choice in most of the networks. However, it has to deploy the Ethernet wires. For the wired internet networks, the power line communication (PLC) technology will be an alternative choice. In this wire-line communication system, the power line network is used as the transmission medium. Therefore, computer networks can work on the existing power line system. No extra new transmission infrastructure is needed. So far, several PLC standards are available, shch as X-10, CEBus(Consumer Electronic Bus), Echonet and Homeplug. This thesis studies the Homeplug AV specification developed by the Homeplug powerline Alliance. By employing MATLAB/Simulink, we build up a PLC baseband transmission model and simulation platform. We carry out the Homeplug AV baseband transmission performance in system level on this platform. The Homeplug AV adopts 3072-point FFT which is not the power of two. It will be a challenge to design the 3072-point FFT processor. Here, we use Xilinx System Generator to design and implement the 3072-point FFT processor. The function verification of the implemented 3072-point FFT processor for Homeplug AV system is carried out by simulation.

As Orthogonal Frequency Division Multiplexing (OFDM) becomes more prevalent in new leading-edge data rate systems processing spectral bandwidths beyond 1 GHz, the required operating speed of the baseband signal processing, specifically the Analog- to-Digital Converter (ADC) and Fast Fourier Transform (FFT) processor, presents significant circuit design challenges and consumes considerable power. Additionally, since Ultra-WideBand (UWB) systems operate in an increasingly crowded wireless environment at low power levels, the ability to tolerate large blocking signals is critical. The goals of this work are to reduce the disproportionately high power consumption found in UWB OFDM receivers while increasing the receiver linearity to better handle blockers. To achieve these goals, an alternate receiver architecture utilizing a new FFT processor is proposed. The new architecture reduces the volume of information passed through the ADC by moving the FFT processor from the digital signal processing (DSP) domain to the discrete time signal processing domain. Doing so offers a reduction in the required ADC bit resolution and increases the overall dynamic range of the UWB OFDM receiver. To explore design trade-offs for the new discrete time (DT) FFT processor, system simulations based on behavioral models of the key functions required for the processor are presented. A new behavioral model of the linear transconductor is introduced to better capture non-idealities and mismatches. The non-idealities of the linear transconductor, the largest contributor of distortion in the processor, are individually varied to determine their sensitivity upon the overall dynamic range of the DT FFT processor. Using these behavioral models, the proposed architecture is validated and guidelines for the circuit design of individual signal processing functions are presented. These results indicate that the DT FFT does not require a high degree of linearity from the linear transconductors or other signal processing functions used in its design. Based on the results of the system simulations, a prototype 8-point DT FFT processor is designed in 130 nm CMOS. The circuit design and layout of each of the circuit functions; serial-to-parallel converter, FFT signal flow graph, and clock generation circuitry is presented. Subsequently, measured results from the first proof-of-concept IC are presented. The measured results show that the architecture performs the FFT required for OFDM demodulation with increased linearity, dynamic range and blocker handling capability while simultaneously reducing overall receiver power consumption. The results demonstrate a dynamic range of 49 dB versus 36 dB for the equivalent all-digital signal processing approach. This improvement in dynamic range increases receiver performance by allowing detection of weak sub-channels attenuated by multipath. The measurements also demonstrate that the processor rejects large narrow-band blockers, while maintaining greater than 40 dB of dynamic range. The processor enables a 10x reduction in power consumption compared to the equivalent all digital processor, as it consumes only 25 mWatts and reduces the required ADC bit depth by four bits, enabling application in hand-held devices. Following the success of the first proof-of-concept IC, a second prototype is designed to incorporate additional functionality and further demonstrate the concept. The second proof-of-concept contains an improved version of the serial-to-parallel converter and clock generation circuitry with the additional function of an equalizer and parallel- to-serial converter. Based on the success of system level behavioral simulations, and improved power consumption and dynamic range measurements from the proof-of-concept IC, this work represents a contribution in the architectural development and circuit design of UWB OFDM receivers. Furthermore, because this work demonstrates the feasibility of discrete time signal processing techniques at 1 GSps, it serves as a foundation that can be used for reducing power consumption and improving performance in a variety of future RF/mixed-signal systems. / Ph. D.

The rapid advancements in semiconductor technology have led to constant shrinking of transistor sizes as per Moore's Law. Wireless communications is one field which has seen explosive growth, thanks to the cramming of more transistors into a single chip. Design of these systems involve trade-offs between performance, area and power. Fast Fourier Transform is an important component in most of the wireless communication systems. FFTs are widely used in applications like OFDM transceivers, Spectrum sensing in Cognitive Radio, Image Processing, Radar Signal Processing etc. FFT is the most compute intensive and time consuming operation in most of the above applications. It is always a challenge to develop an architecture which gives high throughput while reducing the latency without much area overhead. Next generation wireless systems demand high transmission efficiency and hence FFT processor should be capable of doing computations much faster. Architectures based on smaller radices for computing longer FFTs are inefficient. In this thesis, a fully parallel unrolled FFT architecture based on novel radix-4 engine is proposed which is catered for wide range of applications. The radix-4 butterfly unit takes all four inputs in parallel and can selectively produce one out of the four outputs. The proposed architecture uses Radix-4^3 and Radix-4^4 algorithms for computation of various FFTs. The Radix-4^4 block can take all 256 inputs in parallel and can use the select control signals to generate one out of the 256 outputs. In existing Cooley-Tukey architectures, the output from each stage has to be reordered before the next stage can start computation. This needs intermediate storage after each stage. In our architecture, each stage can directly generate the reordered outputs and hence reduce these buffers. A solution for output reordering problem in Radix-4^3 and Radix-4^4 FFT architectures are also discussed in this work. Although the hardware complexity in terms of adders and multipliers are increased in our architecture, a significant reduction in intermediate memory requirement is achieved. FFTs of varying sizes starting from 64 point to 64K point have been implemented in ASIC using UMC 130nm CMOS technology. The data representation used in this work is fixed point format and selected word length is 16 bits to get maximum Signal to Quantization Noise Ratio (SQNR). The architecture has been found to be more suitable for computing FFT of large sizes. For 4096 point and 64K point FFTs, this design gives comparable throughput with considerable reduction in area and latency when compared to the state-of-art implementations. The 64K point FFT architecture resulted in a throughput of 1332 mega samples per second with an area of 171.78 mm^2 and total power of 10.7W at 333 MHz.