The market for battery powered communications devices has grown significantly in recent years. These devices require a large number of analog to digital converters (ADCs) to transform wireless and other physical data into the digital signals required for digital signal processing elements and micro-processors. For these applications, power efficiency and accuracy are of the utmost importance. Successive approximation register (SAR) ADCs are frequently used in power constrained applications, but their main limitation is their low sampling rate. In this work, a two stage pipelined ADC is presented that attempts to mitigate some of the sampling rate limitations of a SAR while maintaining its power and resolution advantages. Special techniques are used to reduce the overall sampling capacitance required in both SAR stages and to increase the linearity of the multiplying digital to analog converter (MDAC) output. The SAR sampling network, control logic, and MDAC blocks are completely implemented. Ideal components were used for the clocking, comparators, and switches. At the end of this design, a figure of merit of 51 fJ/conversion-step was achieved. / text

This dissertation explores methods of reducing the oversampling ratio (OSR) of both delta-sigma modulators and incremental data converters. The first reduced-OSR architecture is the high-order cascaded delta-sigma modulator. These delta-sigma modulators are shown to reduce the in-band noise sufficiently at OSRs as low as 3 while providing power savings. The second low OSR architecture is the high-order cascaded incremental data converter which possesses signal-to-quantization noise ratio (SQNR) advantages over equivalent delta-sigma modulators at low OSRs. The final architecture is the time-interleaved incremental data converter where two designs are identified as potential methods of increasing the throughput of low OSR incremental data converters. A prototype chip is designed in 0.18um CMOS technology which can operate in three modes by simply changing the resetting clock phases. It can operate as an 8-stage pipeline analog-to-digital (A/D) converter, an 8th-order cascaded delta-sigma modulator, and an 8th-order cascaded incremental data converter with an OSR of 3.

Nowadays, the multi-standard wireless receivers and multi-format video processors have created a great demand for integrating multiple standards into a single chip. The multiple standards usually require several Analog to Digital Converters (ADCs) with different specifications. A promising solution is adopting a power and area efficient reconfigurable ADC with tunable bandwidth and dynamic range. The advantage of the reconfigurable ADC over customized ADCs is that its power consumption can be scaled at different specifications, enabling optimized power consumption over a wide range of sampling rates and resulting in a more power efficient design. Moreover, the reconfigurable ADC provides IP reuse, which reduces design efforts, development costs and time to market. On the other hand, software radio transceiver has been introduced to minimize RF blocks and support multiple standards in the same chip. The basic idea is to perform the analog to digital (A/D) and digital to analog (D/A) conversion as close to the antenna as possible. Then the backend digital signal processor (DSP) can be programmed to deal with the digital data. The continuous time (CT) bandpass (BP) sigma-delta ADC with good SNR and low power consumption is a good choice for the software radio transceiver. In this work, a proposed 10-bit reconfigurable ADC is presented and the non-overlapping clock generator and state machine are implemented in UMC 90nm CMOS technology. The state machine generates control signals for each MDAC stage so that the speed can be reconfigured, while the power consumption can be scaled. The measurement results show that the reconfigurable ADC achieved 0.6-200 MSPS speed with 1.9-27 mW power consumption. The ENOB is about 8 bit over the whole speed range. In the second part, a 2-bit quantizer with tunable delay circuit and 2-bit DACs are implemented in TSMC 0.13um CMOS technology for the 4th order CT BP sigma-delta ADC. The 2-bit quantizer and 2-bit DACs have 6dB SNR improvement and better stability over the single bit quantizer and DACs. The penalty is that the linearity of the feedback DACs should be considered carefully so that the nonlinearity doesn't deteriorate the ADC performance. The tunable delay circuit in the quantizer is designed to adjust the excess loop delay up to +/- 10% to achieve stability and optimal performance.

This dissertation explores methods of reducing the oversampling ratio (OSR) of both delta-sigma modulators and incremental data converters. The first reduced-OSR architecture is the high-order cascaded delta-sigma modulator. These delta-sigma modulators are shown to reduce the in-band noise sufficiently at OSRs as low as 3 while providing power savings. The second low OSR architecture is the high-order cascaded incremental data converter which possesses signal-to-quantization noise ratio (SQNR) advantages over equivalent delta-sigma modulators at low OSRs. The final architecture is the time-interleaved incremental data converter where two designs are identified as potential methods of increasing the throughput of low OSR incremental data converters. A prototype chip is designed in 0.18um CMOS technology which can operate in three modes by simply changing the resetting clock phases. It can operate as an 8-stage pipeline analog-to-digital (A/D) converter, an 8th-order cascaded delta-sigma modulator, and an 8th-order cascaded incremental data converter with an OSR of 3.

Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture considered in this work is the current-steering DAC, which is the most commonly used architecture for high-speed applications. Transistor-level simulation of complex circuits using accurate transistor models require long simulation times. A transistor-level model of a DAC used in a system simulation is likely to be a severe bottleneck limiting the overall system simulation speed. Moreover, investigations of stochastic parameter variations require multiple simulation runs with different parameter values making transistor-level models unsuitable. Therefore, there is a need for behavioral-level models with reasonably short simulation times. Behavioral-level models can also be used to find the requirements on different building blocks on high abstraction levels, enabling the use of efficient topdown design methodologies. Models of different nonideal properties in current-steering DACs are used and developed in this work. Static errors typically dominates the low-frequency behavior of the DAC. One of the limiting factors for the static linearity of a current-steering DAC is mismatch between current sources. A well-known model of this problem is used extensively in this work for evaluation of different ideas and techniques for linearity enhancement. The highfrequency behavior of the DAC is typically dominated by dynamic errors. Models oftwo types of dynamic errors are developed in this work. These are the dynamic errors caused by parasitic capacitance in wires and transistors and glitches caused by asymmetry in the settling behavior of a current source. The encoding used for the digital control word in a current steering DAC has a large influence on the circuit performance, e.g., in terms static linearity and glitches. In this work, two DAC architectures are developed. These are denoted the decomposed and partially decomposed architectures and utilize encoding strategies aiming at a high circuit performance by avoiding unnecessary switching of current sources. The developed architectures are compared with the well-known binary-weighted and segmented architectures using behavioral-level simulations. It can be hard to meet a DAC design specification using a straightforward implementation. Techniques for compensation of errors that can be applied to improve the DAC linearity are studied. The well-known dynamic element matching (DEM) techniques are used for transforming spurious tones caused by matching errors into white or shaped noise. An overview of these techniques are given in this work and a DEM technique for the decomposed DAC architecture is developed. In DS modulation, feedback of the quantization error is utilized to spectrally shape the quantization noise to reduce its power within the signal band. A technique based on this principle is developed for spectral shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop. Two examples of utilization of the technique are given. Four different current-steering DACs implemented in CMOS technology are developed to enable comparison between behavioral-level simulations and measurements on actual implementations and to provide platforms for evaluation of different techniques for linearity improvement. For example, a 14-bit DEM DAC is implemented and measurement results are compared with simulation results. A good agreement between measured and simulated results is obtained. Moreover, a configurable 12-bit DAC capable of operating with different degrees of segmentation and decomposition is implemented to evaluate the proposed decomposed architecture. Measurement results agree with results from behavioral-level simulations and indicate that the decomposed architecture is a viable alternative to the commonly used segmented architecture.

Test strategies were developed to reduce the overall production testing cost of high-performance data converters. A static linearity testing methodology, aimed at reducing the test time of A/D converters, was developed. The architectural information of A/D converters was used, and specific codes were measured. To test a high-performance A/D converters using low-performance and low-cost test equipment a dynamic testing methodology was developed. This involved post processing of measurement data. The effect of ground bounce on accuracy of specification measurement was analyzed, and a test strategy to estimate the A/D converter specifications more accurately in presence of ground bounce noise was developed. The proposed test strategies were simulated using behavioral modeling techniques and were implemented on commercially available A/D converter devices. The hardware experiments validated the proposed test strategies. The test cost analysis was done. It suggest that a significant reduction in cost can be obtained by using the proposed test methodologies for data converter production testing.

In this thesis I will present an approach and apparatus for detecting and precisely characterizing any dose-dependent changes in the functional behaviour of a data converter in a neutron radiation environment. Depending on the data converter such changes could include shifts in the gain, offset, noise, or linearity of the device output. The approach leverages the neutron flux produced by an Americium-Beryllium radioisotope neutron source, and is meant to emulate the neutron environment near a Cm-244 source, as found in the sensor head of the APXS instrument. This method uses a relatively low dose rate (configurable by proximity to the source) which allows for long-term monitoring and characterization of parametric changes in device behaviour. It has the additional benefit of not requiring a reactor or accelerator, and can therefore run unattended when necessary. The prototype system, which is designed to allow the data converter to be operating during irradiation, uses LVDS signalling to drive and extract data from a minimal test board which is placed in proximity to the neutron source, and a Virtex-4 FPGA board to provide clock and power, and to perform signal processing. By separating the majority of the test equipment from the neutron environment, any radiation effects will be isolated to the DUT and a minimal set of supporting devices. The prototype design is presented here, along with initial characterization results and first test results on a commercial, off-the-shelf data converter. / Canadian Space Agency, Ontario Centres of Excellence, MacDonald, Dettwiler, and Associates

abstract: High speed current-steering DACs with high linearity are needed in today's applications such as wired and wireless communications, instrumentation, radar, and other direct digital synthesis (DDS) applications. However, a trade-off exists between the speed and resolution of Nyquist rate current-steering DACs. As the resolution increases, more transistor area is required to meet matching requirements for optimal linearity and thus, the overall speed of the DAC is limited. In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB. The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2014

abstract: Semiconductor device scaling has kept up with Moore's law for the past decades and they have been scaling by a factor of half every one and half years. Every new generation of device technology opens up new opportunities and challenges and especially so for analog design. High speed and low gain is characteristic of these processes and hence a tradeoff that can enable to get back gain by trading speed is crucial. This thesis proposes a solution that increases the speed of sampling of a circuit by a factor of three while reducing the specifications on analog blocks and keeping the power nearly constant. The techniques are based on the switched capacitor technique called Correlated Level Shifting. A triple channel Cyclic ADC has been implemented, with each channel working at a sampling frequency of 3.33MS/s and a resolution of 14 bits. The specifications are compared with that based on a traditional architecture to show the superiority of the proposed technique. / Dissertation/Thesis / Ph.D. Electrical Engineering 2012

While data converters have been around for nearly nighty years, mm-wave data converters are still in their infancy. Only recently the 40-GHz sampling barrier was broken with the introduction of the next generation high-speed sampling oscilloscopes. Meanwhile, data communication is the main driving force behind mm-wave data converter development. As with any mm-wave circuit, designers must go beyond simply relying on technology advancement to archives acceptable performance. Careful device and passive modeling is critical and systematic design methodology may o er repeatable and scalable mm-wave designs. In this thesis the design methodology and architectural challenges of mm-wave ADCs are explored. Some of the fundamental mm-wave ADC building blocks such as track and hold ampli ers, data distribution networks and ip- ops are implemented in SiGe BiCMOS and CMOS technologies and characterized. Several record breaking circuits are presented along with systematic design methodology. The impact of these circuit blocks on the performance of the next generation ADCs is studied and experimentally veri ed using a 35-GS/s, 4-bit ADC-DAC chain implemented in a SiGe BiCMOS technology.