Orientador: Marco-Aurelio De Paoli / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Quimica / Made available in DSpace on 2018-08-04T22:57:56Z (GMT). No. of bitstreams: 1 Freitas_JilianNeide_M.pdf: 8316699 bytes, checksum: 55e34d22b75f9c9b873f2edbf8cba703 (MD5) Previous issue date: 2005 / Resumo: Investigaram-se células solares de TiO2/corante e eletrólito polimérico visando a construção de um módulo de 9 V. O filme de TiO2 depositado sobre substratos de FTO (fIuorine tin oxide) em vidro foi obtido a partir da modificação de uma suspensão comercial do óxido coloidal em água. Para obter um filme com bom desempenho, utilizou-se uma suspensão com 0,45 g mL à qual foi adicionado 33 % (m/m) de polietilenoglicol com massa molar 20000. O eletrólito empregado nas células consistiu de Nal e I2 dissolvidos em poli(óxido de etileno-co-epicloridrina) contendo os co-monômeros na proporção 87:13, respectivamente. A condutividade iônica máxima desse sistema ocorreu para uma concentração de sal de 15 % (m/m) em relação à matriz polimérica; 2,7 x 10 S cm sob umidade < 1,0 ppm e ~ 30°C. Com o objetivo de aumentar a condutividade iônica, adicionou-se g-butirolactona como plastificante, mantendo-se a concentração de sal em relação à massa de polímero. Observou-se um aumento de cerca de uma ordem de grandeza na condutividade iônica e no coeficiente de difusão das espécies eletroativas no eletrólito plastificado. A suspensão de TiO2 e o eletrólito otimizados foram utilizados na preparação de células solares com área ativa de 1,0 e 4,5 cm. As células menores foram irradiadas com uma lâmpada de Xe. Sob 10 mW cm foram obtidas eficiências de conversão de energia de 2-3 %. As células com área ativa maior foram caracterizadas diretamente sob o Sol e apresentaram eficiência média de 0,9 % (às 12 h). Estes dispositivos foram usados na montagem de módulos de16 células conectadas em série, produzindo 9 V de potencial e 183 mW (valor integrado em um dia). Em conclusão este trabalho demonstrou que, é possível construir um módulo com células solares de TiO2/corante preparadas com eletrólito polimérico plastificado. O desempenho do módulo excedeu as expectativas, sendo a estabilidade o principal desafio para permitir a sua futura aplicação em escala comercial. / Abstract: TiO2 dye-sensitized solar cells assembled with polymer electrolyte were investigated aiming at the construction of a 9 V module. The TiO2 film deposited on substrates of FTO (fluorine tin oxide) on glass was obtained through the modification of a colloidal oxide suspension in water . To obtain a film with good performance, a suspension containing 0.45 g mL of TiO2 and 33 wt % of polyethyleneglycol with molar weight of 20000 was employed. The electrolyte consisted of Nal and I2 dissolved in poly(ethylene oxide-co-epichlorydrin) containing the monomers in the molar ratio 87:13. The maximum ionic conductivity for this system occurred for a concentration of salt of 15 wt % in relation to the polymer matrix; 2.7 x 10 S cm under relative humidity lower than 1.0 ppm and 30°C. To increase the ionic conductivity, g-butyrolactone was added to the electrolyte as a plasticizer, maintaining the salt concentration constant in relation to the polymer. The measured ionic conductivity and diffusion coefficient for the plasticized electrolyte were both increased by ca. one order of magnitude. Both, optimized TiO2 suspension and electrolyte, were applied in solar cells assembled with active area of 1.0 or 4.5 cm. The smaller cells were investigated under 10 mW cm irradiation, with a Xe lamp, and the efficiency of energy conversion was 23 %. The larger cells were characterized directly under the Sun with an average efficiency of 0.9 % (at 12:00 h). These were used to assemble a 9 V module by connecting in series 16 cells. The integrated average daily power was 183 mW. In summary, this work demonstrated that it is feasible to assemble a module with dyesensitized solar cells employing a plasticized polymer electrolyte. The performance of the modules exceeded all expectations and their stability is the main challenge to allow a future commercial scale application. / Mestrado / Quimica Inorganica / Mestre em Química

Submitted by Divisão de Documentação/BC Biblioteca Central (ddbc@ufam.edu.br) on 2017-02-07T17:47:31Z No. of bitstreams: 2 license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Dissertação - Mário A. P. Garcia.pdf: 1777955 bytes, checksum: bbc5f97c856505f518492e5c8ec65c28 (MD5) / Approved for entry into archive by Divisão de Documentação/BC Biblioteca Central (ddbc@ufam.edu.br) on 2017-02-07T17:47:47Z (GMT) No. of bitstreams: 2 license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Dissertação - Mário A. P. Garcia.pdf: 1777955 bytes, checksum: bbc5f97c856505f518492e5c8ec65c28 (MD5) / Approved for entry into archive by Divisão de Documentação/BC Biblioteca Central (ddbc@ufam.edu.br) on 2017-02-07T17:48:08Z (GMT) No. of bitstreams: 2 license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Dissertação - Mário A. P. Garcia.pdf: 1777955 bytes, checksum: bbc5f97c856505f518492e5c8ec65c28 (MD5) / Made available in DSpace on 2017-02-07T17:48:08Z (GMT). No. of bitstreams: 2 license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Dissertação - Mário A. P. Garcia.pdf: 1777955 bytes, checksum: bbc5f97c856505f518492e5c8ec65c28 (MD5) Previous issue date: 2016-09-13 / CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / The software development for embedded systems is getting faster and faster, which generally incurs an increase in the associated complexity. As a consequence, consumer electronics companies usually invest a lot of resources in fast and automatic verification mechanisms, in order to create robust systems and reduce product recall rates. In addition, further development-time reduction and system robustness can be achieved through cross-platform frameworks, such as Qt, which favor the reliable port of software stacks to different devices. Based on that, the present work proposes a simplified version of the Qt framework, which is integrated into a checker based on satisfiability modulo theories (SMT), name as the efficient SMT-based bounded model checker (ESBMC++), for verifying actual Qt-based applications, and presents a success rate of 89%, for the developed benchmark suite. We also evaluate our simplified version of the Qt framework using other state-of-the-art verifiers for C++ programs and an evaluation about their level of compliance. It is worth mentioning that the proposed methodology is the first one to formally verify Qt-based applications, which has the potential to devise new directions for software verification of portable code. / O desenvolvimento de software para sistemas embarcados tem crescido rapidamente, o que na maioria das vezes acarreta em um aumento da complexidade associada a esse tipo de projeto. Como consequência, as empresas de eletrônica de consumo costumam investir recursos em mecanismos de verificação rápida e automática, com o intuito de desenvolver sistemas robustos e assim reduzir as taxas de recall de produtos. Além disso, a redução no tempo de desenvolvimento e na robustez dos sistemas desenvolvidos podem ser alcançados através de frameworks multi-plataformas, tais como Qt, que oferece um conjunto de bibliotecas (gráficas) confiáveis para vários dispositivos embarcados. Desta forma, este trabalho propõe uma versão simplificada do framework Qt que integrado a um verificador baseado nas teorias do módulo da satisfatibilidade, denominado Efficient SMT-Based Bounded Model Checker (ESBMC++), verifica aplicações reais que ultilizam o Qt, apresentando uma taxa de sucesso de 89%, para os benchmarks desenvolvidos. Com a versão simplificada do framework Qt proposto, também foi feita uma avaliação ultilizando outros verificadores que se encontram no estado da arte para verificação de programas em C++ e uma avalição a cerca de seu nível de conformidade. Dessa maneira, a metodologia proposta se afirma como a primeira a verificar formalmente aplicações baseadas no framework Qt, além de possuir um potencial para desenvolver novas frentes para a verificação de código portátil.

Made available in DSpace on 2014-06-12T23:15:57Z (GMT). No. of bitstreams: 2 arquivo8636_1.pdf: 5881597 bytes, checksum: 2b491d2b1781f9e685a098c689a1d34c (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2008 / Conhecer com maior profundidade o efeito da temperatura na energia gerada por módulos fotovoltaicos submetidos a condições climáticas variadas é o foco deste trabalho. Com este objetivo, foram estudados diversos modelos propostos na literatura e definido o modelo de cinco parâmetros como o mais apropriado para a caracterização das células fotovoltaicas. Estabelecida a base conceitual, foi desenvolvida uma ferramenta de engenharia, de fácil utilização, que permite a partir dos dados climáticos medidos em campo, ou simulados, conhecer o comportamento do módulo, obtendo inclusive a energia final produzida em um dado intervalo de tempo. A ferramenta foi aplicada inicialmente para traçar a curva característica de um módulo da tecnologia silício monocristalino. A comparação entre as curvas traçadas com as curvas fornecidas pelos fabricantes consolidou o modelo e a metodologia adotados. A seguir, foi avaliado o desempenho de um módulo fotovoltaico fabricado com a tecnologia de silício monocristalino caso fosse instalado em Recife e Araripina, representando respectivamente a região litorânea e o Sertão de Pernambuco. Os resultados obtidos confirmaram a expectativa gerada a partir de estudos anteriores, e permitiram identificar que a opção de instalar o módulo em Araripina ao invés de Recife implica no aumento do desempenho em 10%, devido às condições climáticas locais distintas, o que é bastante significativo na geração de energia de sistemas de grande porte. Finalmente, foram feitas simulações para módulos das tecnologias de silício policristalino, silício amorfo e células de películas finas. A consistência dos resultados confirmou o uso da ferramenta de engenharia para estas tecnologias, e permitiu avaliar o efeito da temperatura no desempenho dos módulos

The purpose of the thesis was to study the feasibility of using geneticalgorithm (GA) to do the integrated software pipelining (ISP). Different from phasedcode generation, ISP is a technique which integrates instruction selection, instructionscheduling, and register allocation together when doing code generation. ISP is able toprovide a lager solution space than phased way does, which means that ISP haspotential to generate more optimized code than phased code generation. However,integrated compiling costs more than phased compiling. GA is stochastic beam searchalgorithm which can accelerate the solution searching and find an optimized result.An experiment was designed for verifying feasibility of implementing GA for ISP(GASP). The implemented algorithm analyzed data dependency graphs of loop bodies,created genes for the graphs and evolved, generated schedules, calculated andevaluated fitness, and obtained optimized codes. The fitness calculation wasimplemented by calculating the maximum value between the smallest possibleresource initiation interval and the smallest possible recurrence initiation interval. Theexperiment was conducted by generating codes from data dependency graphsprovided in FFMPEG and comparing the performance between GASP and integerlinear programming (ILP). The results showed that out of eleven cases that ILP hadgenerated code, GASP performed close to ILP in seven cases. In all twelve cases thatILP did not have result, GASP did generate optimized code. To conclude, the studyindicated that GA was feasible of being implemented for ISP. The generated codesfrom GASP performed similar with the codes from ILP. And for the dependencygraphs that ILP could not solve in a limited time, GASP could also generate optimizedresults.

Satisfiability (SAT) and satisfiability modulo theories (SMT) solvers are high-performance automated propositional and first-order theorem provers, used as underlying tools in many formal verification and artificial intelligence systems. Theoretic and engineering advancement of solver technologies improved the performance of modern solvers; however, the increased complexity of those solvers calls for formal verification of those tools themselves. This thesis discusses two methods to formally certify SAT/SMT solvers. The first method is generating proofs from solvers and certifying those proofs. Because new theories are constantly added to SMT solvers, a flexible framework to safely add new inference rules is necessary. The proposal is to use a meta-language called LFSC, which is based on Edinburgh Logical Framework. SAT/SMT logics have been encoded in LFSC, and the encoding can be easily and modularly extended for new logics. It is shown that an optimized LFSC checker can certify SMT proofs efficiently. The second method is using a verified programming language to implement a SAT solver and verify the code statically. Guru is a pure functional programming language with support for dependent types and theorem proving; Guru also allows for efficient code generation by means of resource typing. A modern SAT solver, called versat, has been implemented and verified to be correct in Guru. The performance of versat is shown to be comparable with that of the current proof checking technology.

Many bugs are reported during the software maintenance phase, and in order for asoftware product to have a longer life, it must effectively handle and resolve thesebugs. As a result, when cost and time are considered, a prioritized list of bugs isrequired for all products. Due to some factors, such as user expertise, the numberof bugs, the priority methodology, and how critical the software is, developing a prioritization technique that includes user inputs and preset bug constraints to producea final prioritization list of software bugs is challenging. Our approach to solvingthe prioritization problem involves combining an SMT solver with user interactionto provide the best possible solution. Our findings suggest that this strategy outperforms both random and non-interactive bug prioritization methods.

Prioritization of software requirements is an important part of the requirements engineering process within the industry of software development. There are many different methods for achieving the most optimal order of software requirements, a list that shows in what order the requirements should be implemented. This degree project utilizes the SMT-based solver Z3 for an interactive prioritization algorithm. Previous studies have shown good results with another SMT-based solver called Yices. With the newer Z3 from Microsoft, the results have been improved further, and the tool is based on Python, and the framework for Z3 is called Z3PY. Experiments have been conducted on a set of different software requirements derived from a project in the healthcare industry and show that the Z3 solution is, in general, improving the requirements prioritization compared to other mentioned solutions in the study that has been tested on the same set of requirements. Results show that the Z3 solution outperformed the other SMT-based solution Yices by 2-4% regarding disagreement and by 3% regarding average distance. The results are significantly improved based on an ANOVA test with a p-value &lt;= 0.05.

With the advent of advanced program analysis and constraint solving techniques, several test generation tools use variants of symbolic execution. Symbolic techniques have been shown to be very effective in path-based test generation; however, they fail to scale to large programs due to the exponential number of paths to be explored. In this thesis, we focus on tackling this path explosion problem and propose search strategies to achieve quick branch coverage under symbolic execution, while exploring only a fraction of paths in the program. We present a reachability-guided strategy that makes use of the reachability graph of the program to explore unvisited portions of the program and a conflict driven backtracking strategy that utilizes conflict analysis to perform nonchronological backtracking. We also propose error-directed search strategies, that are aimed at catching bugs in the program faster, by targeting those parts of the program where bugs are likely to be found or those that are hard to reach. We present experimental evidence that these strategies can significantly reduce the search space and improve the speed of test generation for programs. / Master of Science

Over the last two decades, chip design has been conducted at the register transfer (RT) Level using Hardware Descriptive Languages (HDL), such as VHDL and Verilog. The modeling at the behavioral level not only allows for better representation and understanding of the design, but also allows for encapsulation of the sub-modules as well, thus increasing productivity. Despite these benefits, validating a RTL design is not necessarily easier. Today, design validation is considered one of the most time and resource consuming aspects of hardware design. The high costs associated with late detection of bugs can be enormous. Together with stringent time to market factors, the need to guarantee the correct functionality of the design is more critical than ever. The work done in this thesis tackles the problem of RTL design validation and presents new frameworks for functional test generation. We use branch coverage as our metric to evaluate the quality of the generated test stimuli. The initial effort for test generation utilized simulation based techniques because of their scalability with design size and ease of use. However, simulation based methods work on input spaces rather than the DUT's state space and often fail to traverse very narrow search paths in large input spaces. To encounter this problem and enhance the ability of test generation framework, in the following work in this thesis, certain design semantics are statically extracted and recurrence relationships between different variables are mined. Information such as relations among variables and loops can be extremely valuable from test generation point of view. The simulation based method is hybridized with Z3 based symbolic backward execution engine with feedback among different stages. The hybridized method performs loop abstraction and is able to traverse narrow design paths without performing costly circuit analysis or explicit loop unrolling. Also structural and functional unreachable branches are identified during the process of test generation. Experimental results show that the proposed techniques are able to achieve high branch coverage on several ITC'99 benchmark circuits and their modified variants, with significant speed up and reduction in the sequence length. / Master of Science

Many critical systems are based on the combination of components from different physical domains (e.g. mechanical, electrical, hydraulic), and are mathematically modeled as Switched Multi-Domain Kirchhoff Networks (SMDKN). In this thesis, we tackle a major obstacle to formal verification of SMDKN, namely devising a global model amenable to verification in the form of a Hybrid Automaton. This requires the combination of the local dynamics of the components, expressed as Differential Algebraic Equations, according to Kirchhoff's laws, depending on the (exponentially many) operation modes of the network. We propose an automated SMT-based method to analyze networks from multiple physical domains, detecting which modes induce invalid (i.e. inconsistent) constraints, and to produce a Hybrid Automaton model that accurately describes, in terms of Ordinary Differential Equations, the system evolution in the valid modes, catching also the possible non-deterministic behaviors. The experimental evaluation demonstrates that the proposed approach allows several complex multi-domain systems to be formally analyzed and model checked against various system requirements.