In this study, we have considered the modal and non-modal stability of fluids with shear-dependent viscosity flowing in a rigid straight pipe. A second order finite-difference code is used for the simulation of pipe flow in the cylindrical coordinate system. The Carreau-Yasuda model where the rheological parameters vary in the range of 0.3 < n < 1.5 and 0.1 < λ < 100 is represents the viscosity of shear- thinning and shear thickening fluids. Variation of the periodic pulsatile forcing is obtained via the ratio Kω/Kο and set between 0.2 and 20. Zero and non-zero streamwise wavenumber have been considered separately in this study. For the axially invariant mode, energy growth maxima occur for unity azimuthal wave number, whereas for the axially non-invariant mode, maximum energy growth can be observed for azimuthal wave number of two for both Newtonian and non-Newtonian fluids. Modal and non-modal analysis for both Newtonian and non-Newtonian fluids show that the flow is asymptotically stable for any configuration and the pulsatile flow is slightly more stable than steady flow. Increasing the maximum velocity for shear-thinning fluids caused by reducing power-low index n is more evident than shear-thickening fluids. Moreover, rheological parameters of Carreau-Yasuda model have ignored the effect on the peak velocity of the oscillatory components. Increasing Reynolds number will enhance the maximum energy growth while a revers behavior is observed by increasing Womersley number.

The objectives of this research lie in the area of millimeter and submillimeter wave signal generation and are directed into two paths that are separate, but related. The first involves the development of a W-Band oscillator using Raytheon's Metamorphic High Electron Mobility Transistor (MHEMT) substrate. The second involves the development of silicon formed rectangular waveguide to replace metallic waveguide, ultimately to be used in THz signal source circuits. An exploration of two different topologies for a W-Band oscillator design utilizing Raytheon s MHEMT substrate is presented. This material will demonstrate the reasoning behind the topology selection and the approach of the design. An evaluation of this first ever W-Band MHEMT oscillator will be presented demonstrating its performance capabilities. Finally, an oscillator design will be presented extending the first successful MHEMT W-Band design. The area of Silicon rectangular waveguide with is covered. A design approach of the silicon waveguide will be discussed. The technology used to fabricate and package the silicon waveguide will be explained. The results of the very first 400 GHz silicon waveguide will be shown and the future efforts will be covered. A silicon micromachined waveguide multiplier using an HBV diode circuit is constructed and successfully demonstrated with an output frequency of 261 GHz, showing little difference between using micromachined waveguide and metal waveguide. Lastly, a power combining frequency multiplier is developed utilizing HBV diodes with an output of 260 GHz. The input and output sections are created using branch line couplers. The results showed good power generation as compared to a single diode multiplier.

The communication technology is changing rapidly every day, and the internet has played a very important role in our lives. Through specific protocols, people transform the data into 0¡¦s and 1¡¦s as digital signals and transfer them from sender to receiver via the network. Unfortunately, data transfer through the internet is open to the public, and too much exposure of private data may be a serious risk. To avoid this situation, we can encrypt the data before transmission to guarantee data confidentiality and privacy. The RSA encryption system is a simple and highly secure public key cryptosystem, but the encryption and decryption process requires a lot of exponentiation operations and division operations. In order to improve the reliability of the encrypted data, the operands are usually larger than 512 bits. If software is used to perform encryption and decryption, real time application will not be sufficed, since software lacks performance. For this reason, the RSA must be implemented in hardware. Since then, many methods of refining the effectiveness of the RSA encryption and decryption hardware have began to be developed. This research proposes a new Modular Multiplier architecture similar to the original Montgomery Modular Multiplier and the RSA encryption system, which is composed by simple adders, shifting registers and multiplexers. What¡¦s more, we¡¦ve also proposed new concepts including the Quotient Lookahead and the Superfluous Operation Elimination to further enhance the performance. The test results show that our design can reduce the total cycle count by 19%, and also save the overall energy consumption. Due to the features of high performance and energy saving, the proposed design is suitable for portable devices which have low power requirements.

The explosive growth in the data communications industry has positioned the internet to hold very important roles in our lives. Sending or receiving data on an open network is an invitation for unauthorized users to obtain your personal information. In order to avoid compromising sensitive information while transferring data, the data needs to be encrypted before transmission to ensure that the information remains safe and confidential. RSA is the most widely used public-key cryptosystem. An RSA operation is a modular exponentiation, which is usually achieved by repeated modular multiplications. For security reasons, RSA operand sizes need to be 512 bits or greater. It would be difficult to achieve real time transmission on the internet by running software programs on typical processors. For this reason, we believe it is necessary to implement RSA by hardware circuit in order to speed up RSA operations. Modular exponentiation is the only operation in RSA cryptosystem and it can be done through repeated modular multiplications. The Montgomery multiplication algorithm is widely recognized as the most efficient modular multiplication algorithm. In order to improve the speed of RSA operation, many papers have proposed ways to refine the Montgomery Algorithm and its architecture. In this thesis, we focus on further improving the performance and power consumption of RSA cryptosystems. This research presents an improved Montgomery multiplier and RSA cryptosystem architecture using only one carry saver adder to significantly reduce the delays of conventional multipliers. We also proposed a low power shift register to reduce power consumption of shift register in Montgomery multiplier. Experimental results show that the proposed RSA cryptosystem not only runs with higher performance but also consumes less power, leading to this system more competitive and suitable for implementations in portable electronic products.

Thanks to the development of the Internet in recent years, we can see more and more applications on E-commerce in the world. At the same time, we have to prevent our personal information to be leaked out during the transaction. Therefore, topic on researching network security becomes increasingly popular. It is well-known that an encryption system can be applied to consolidate the network security. RSA encryption algorithm is a special kind of asymmetric cryptography, commonly used in public key encryption system on the network, by using two prime numbers as the two keys to encrypt and decrypt. These two keys are called public key and private key, and the key length is at least 512 bits. As a public key encryption, the only way to decrypt is using the private key. As long as the private key is not revealed, it is very difficult to get the private key from the public key even using the reverse engineering. Therefore, RSA encryption algorithm can be regarded as a very safe encryption and decryption algorithm. As the minimum key length has to be greater than 512 bits to ensure information security, using software to execute RSA encryption and decryption will be very slow so that the real time requirement may not be satisfied. Hence we will have to implement RSA encryption system with a hardware circuit to meet the real time requirement on the network. Modular exponentiation (i.e., ME mod N) in RSA cryptosystem is usually achieved by repeated modular multiplications on large integers. A famous approach to implement the modular multiplication into hardware circuits is based on the Montgomery modular multiplication algorithm, which replaces the trial division by modulus with a series of addition and shift operations. However, a large amount of clock cycle is still required to complete a modular multiplication. For example, Montgomery multiplication algorithm will take 512 clock cycles to complete an A․B mod N. As a result, performing one modular exponentiation ME mod N in RSA cryptosystm will need 512․512 clock cycles. To counter the above disadvantage, we employ radix-4 algorithm to reduce 50% of clock cycle number for each A•B mod N. In addition, we also modify the architecture of conventional in order to achieve the radix-4 algorithm to reduce its critical path delay so that the performance can be improved further. Experimental results show that the proposed 1024-bit radix-4 modular multiplier (Our-Booth-Radix-4) before performing as pipeline is 70% faster than the radix-2 multiplier with 24% area overhead. Furthermore, it is 20% faster than traditional radix-4 modular multiplier with 12% area reduction. Therefore, its AT is smaller than the previous architectures.

The financial tsunami struck the entire world in 2008, leading to global economic downturn and unprecedented loss in the global financial markets. In an already weakened economic environment, investors continued to lose confidence, unemployment soared to an all time high and consumer spending continued to shrink. Thus economic growth continued to spiral downward. After careful consideration of all economic indicators and approaches taken by other countries, the Taiwan government launched the Consumption Voucher Policy in a short period of time. The government launched a variety of economic stimulus packages to revive the economy and restore economic growth as quickly as possible. To make distribution of consumption vouchers in the amount of NTD 3,600 dollars to each person, for which was to be spent within a short period of time, and it was estimated to add 0.66 percent on the economic growth of 2009. The issuance of the consumption voucher which helped to stop the economic free fall by encouraging consumer spending, also demonstrated government efficiency and exhibited cooperation among government authorities and people. The scope of this study is focusing on the causes and effectiveness of the program, and summarizing the data collected to record the first issuance of consumption vouchers.

Currently, data size that we have to deal with is growing bigger and bigger. This fact implies that the computing time and computing power for dealing with the data is demanded. A way to circumvent the difficulty is as follows: Divide the data into several small blocks and then process these small blocks by several computers. Therefore, we need a tool for the decomposition-coordinated procedure. Alternating direction method of multipliers (ADMM) is a powerful algorithm for the mentioned purpose and has widely used in distributed optimizations. With ADMM algorithm, a big global optimization problem can be decomposed into several small local optimization problems. ADMM algorithm has been used in several recent distributed systems such as cloud systems and distributed antenna systems. In this thesis, we aim to apply the ADMM in a distributed antenna system. For the uplink setting, we develop a distributed demodulation algorithm, where multiple base stations collaborate with each other for data detection. On the other hand, for the downlink setting, we develop a distributed beamforming design algorithm, where multiple base stations collaborate to form a beamforming for mitigating the inter-cell interference. Finally, simulations are conducted to verify the efficiency of our designs.

This thesis includes two research topics. The first topic is a low-power 2-dimensional bypassing digital multiplier design. The second one is a low-power sensorless micro-controller for brushless DC motors (BLDCM). The low-power 2-dimensional bypassing digital multiplier takes advantage of a 2-dimensional bypassing method. The proposed bypassing cells constituting the multiplier skip redundant signal transitions when the horizontally partial product or the vertically operand is zero. Hence, it is a 2-dimensional bypassing architecture. Thorough post-layout simulations show that the power dissipation of the proposed 8 ¡Ñ 8 design is reduced by more than 75% compared to the prior 8 ¡Ñ 8 design with obscure cost of delay and area. The goal of the low-power sensorless micro-controller for brushless DC motors is to design a BLDCM controller without using any Hall sensor. Back-EMF estimation method using the terminal voltage sensing is adopted for the detection of the commutation moment for the proper commutation control of the BLDCM. The position of the rotor can be precisely estimated by measuring the back-EMF as well as the zero-crossing points.

Optical communications is expanding into new applications such as infrared wireless communications; therefore, designing high performance circuits has gained considerable importance. In this dissertation a wide dynamic-range variable-gain transimpedance amplifier (TIA) is introduced. It adopts a regulated cascode (RGC) amplifier and an operational transconductance amplifier (OTA) as the feed forward gain element to control gain and improve the overload of the optical receiver. A fully-differential variable-gain TIA in a 0.35µm CMOS technology is realized. It provides a bit error rate (BER) less than 10-12 for an input current from 6µA-3mA at 3.3V power supply. For the transimpedance gain variation, from 0.1kΩ to 3kΩ, -3dB bandwidth is higher than 1.7GHz for a 0.6pF photodiode capacitance. The power dissipations for the highest and the lowest gains are 8.2mW and 24.9mW respectively. A new technique for designing uniform multistage amplifiers (MA) for high frequency applications is introduced. The proposed method uses the multi-peak bandwidth enhancement technique while it employs identical, simple and inductorless stages. It has several advantages, such as tunability of bandwidth and decreased sensitivity of amplifier stages, to process variations. While all stages of the proposed MA topology are identical, the gain-bandwidth product can be extended several times. Two six-stage amplifiers in a TSMC 0.35µm CMOS process were designed using the proposed topology. Measurements show that the gain can be varied for the first one between 16dB and 44dB within the 0.7-3.2GHz bandwidth and for the second one between 13dB and 44dB within a 1.9-3.7GHz bandwidth with less than 5.2nV/√Hz noise. Although the second amplifier has a higher gain bandwidth product, it consumes more power and occupies a wider area. A technique for capacitance multiplication is utilized to design a tunable loop filter. Current and voltage mode techniques are combined to increase the multiplication factor (M). At a high input dynamic range, M is adjustable and the capacitance multiplier performs linearly at high frequencies. Drain-source voltages of paired transistors are equalized to improve matching in the current mirrors. Measurement of a prototype loop filter IC in a 0.5µm CMOS technology shows 50µA current consumption for M=50. Where 80pF capacitance is employed, the capacitance multiplier realizes an effective capacitance varying from 1.22nF up to 8.5nF.

Floating-point multipliers are typically power hungry which is undesirable in many embedded applications. This paper proposes a variable-latency floating-point multiplier architecture, which is suitable for low-power, high-performance, and high-accuracy applications. The architecture splits the significand multiplier into upper and lower parts, and predicts the required significand product and sticky bit from upper part. In the case of correct prediction, the computation of lower part is disabled and the rounding operation is significantly simplified so that floating-point multiplication can be completed early. Finally, detailed design and simulation of the floating-point multiplier is presented, together with its evaluation by comparing power consumption with the fast and conventional floating-point multipliers. Experimental results demonstrate that the proposed double-precision multiplier consumes up to 26.41% and 24.97% less power and energy than the fast floating-point multiplier respectively at the expense of only small area and delay overhead. In addition, the results also show that the performance of proposed floating-point multiplier is very approximate to that of fast floating-point multipliers.