This thesis includes two topics. The first topic is a programmable DLL-based frequency multiplier, which can be a local oscillator in RF applications. The second one is a ROM-less direct digital frequency synthesizer to serve as a good reference clock or to be used in digital modulation and demodulation. A CMOS local oscillator using a programmable DLL-based frequency multiplier is presented. In this work, low-Q on-chip inductors are not needed. The clock of the output frequency is digitally controllable, which is ranged from 7´ to 10´ of an input reference clock. The design is carried out by TSMC 1P5M 0.25 mm CMOS process at 2.5 V power supply. The output frequency range of the physical chips measurement is about 1.0 GHz ~ 1.5 GHz. Maximum power dissipation is 58.2 mW at 1.5 GHz output. A ROM-less direct digital frequency synthesizer (DDFS) employing trigonometric quadruple angle formula is presented. In a system-level simulation, the spurious tones performance is suppressed to be lower than -130 dBc. The resolution is up to 13 bits. The maximum error is also analyzed mathematically to meet the simulation results.

Unmanned Vehicles (UVs) have been significantly utilized in military and civil applications over the last decade. Path-planning of UVs plays an important role in effectively using the available resources such as the UVs and sensors as efficiently as possible. The main purpose of this thesis is to address two path planning problems involving a single UV. The two problems we consider are the quota problem and the budget problem. In the quota problem, the vehicle has to visit a sufficient number of targets to satisfy the quota requirement on the total prize collected in the tour. In the budget problem, the vehicle has to comply with a constraint of the distance traveled by the UV. We solve both these problems using a practical heuristic called the prize-multiplier approach. This approach first uses a primal-dual algorithm to first assign the targets to the UV. The Lin – Kernighan Heuristic (LKH) is then applied to generate a tour of the assigned targets for the UV. We tested this approach on two different vehicle models. One model is a simple vehicle which can move in any direction without a constraint on its turning radius. The other model is a Reeds-Shepp vehicle. We also modeled both problems in C++ using the multi-commodity flow formulations, and solved them to optimality by using the Concert Technology of CPLEX. We used the results generated by CPLEX to determine the quality of the solutions produced by the heuristics. By comparing the objective values of the obtained solutions and the running times of the heuristics and CPLEX, one can conclude that the proposed heuristics produce solutions with good quality to our problems within our desired time limits.

In this paper, new software and hardware designs for the NTRU Public Key Cryptosystem are proposed. The first design attempts to improve NTRU's polynomial multiplication through applying techniques from the Chinese Remainder Theorem (CRT) to the convolution algorithm. Although the application of CRT shows promise for the creation of the inverse polynomials in the setup procedure, it does not provide any benefits to the procedures that are critical to the performance of NTRU (public key creation, encryption, and decryption). This research has identified that this is due to the small coefficients of one of the operands, which can be a common misunderstanding. The second design focuses on improving the performance of the polynomial multiplications within NTRU's key creation, encryption, and decryption procedures through hardware. This design exploits the inherent parallelism within a polynomial multiplication to make scalability possible. The advantage scalability provides is that it allows the user to customize the design for low and high power applications. In addition, the support for arbitrary precision allows the user to meet the desired security level. The third design utilizes the Montgomery Multiplication algorithm to develop an unified architecture that can perform a modular multiplication for GF(p) and GF(2^k) and a polynomial multiplication for NTRU. The unified design only requires an additional 10 gates in order for the Montgomery Multiplier core to compute the polynomial multiplication for NTRU. However, this added support for NTRU presents some restrictions on the supported lengths of the moduli and on the chosen value for the residue for the GF(p) and GF(2^k) cases. Despite these restrictions, this unified architecture is now capable of supporting public key operations for the majority of Public-Key Cryptosystems.

This dissertation contributes to the field of health economics, which, in the past couple of decades, has substantially increased our understanding of the determinants of human health, health-related behavior, and health care choices. A large body of literature has documented the influence of peer group behavior on individual choices. The purpose of my research is to examine the extent of such a phenomenon in breast cancer preventive behavior. Using Behavioral Risk Factors Surveillance System (BRFSS) surveys from 1993-2008, I measured the effect of other female screening behavior on an individual's decision to have a routine breast cancer screening by calculating the size of a so called social multiplier in mammography. I estimated a vector of social multipliers in the use of annual mammograms by taking the ratio of group-level effects of exogenous explanatory variables to individual-level effects of the same variables. Peer groups are defined as same-aged women living in the same geographical area: county or state. Several econometric methods were used to analyze the effect of social interactions on decision to undergo mammography, including ordinary least squares, fixed effects, the split sample instrumental variable approach, and a falsification test. My results supported the hypothesis that social interactions have an impact on the decision to have a mammogram. For all women over age 40, I found strong evidence of social interactions being associated with individual's education and ethnicity. In addition, the decision for women ages 40-49 to have a screening was subject to peer influence through their place of employment and ownership of health insurance. Finally, for women age 75 and older, being married and aging were the most important channels through which peer group influenced the decision to have a mammogram. This research has important policy implications in the presence of current health care reform that reimburses breast cancer screening at 100%, while rates of mammography receipt remain below the policy goal. Furthermore, I examined the effect of the 2009 United States Preventive Services Task Force change in screening recommendations on screening behavior. I demonstrated an immediate reduction in the receipt of mammography among women of all age groups following the revision of screening guidelines. I found that in 2010, the twelve month mammography receipt decreased by 1.97 (women ages 40-49), 2.20 (ages 50-74), and 3.61 (age 75 and older) percentage points, and the twenty-four months mammography receipt decreased by 1.47 (women ages 40-49), 1.05 (ages 50-74), and 1.92 (age 75 and older) percentage points. Analysis using a two-year follow up period after the revision of screening recommendations provided further support to this conclusion.

ABSTRACT Due to the rapid progress in the field of VLSI, improvements in speed, power and area are quite evident. Research and development in this field are motivated by growing markets of portable mobile devices such as personal multimedia players, cellular phones, digital camcorders and digital cameras. Among the recently popular logic families, pass transistor logic is promising for low power applications as compared to conventional static CMOS because of lower transistor count. This thesis proposes four novel designs for Booth encoder and selector logic using pass logic principles. These new designs are implemented and used to build a 64 x 64-bit multiplier. The proposed Booth encoder and selector logic are competitive with the existing and shows substantial reduction in transistor count. It also shows improvements in delay when compared to two of the three published works.

The arithmetic operations in most digital system are in the conventional binary number systems. However, the finite field arithmetic has also been widely used in applications of cryptography and communication channel coding. For example, finite field constant multiplication is applied to the advanced encryption standard (AES) and in the Reel-Solomon code. In this thesis, we develop a synthesizer that can automatically generate optimized gate-level netlists for constant matrix multiplication in Galois Field GF(2^n). The logic minimization is based on the a new common-factor elimination (CSE) algorithm that can efficiently finds the shared common factors among all the bit-level Boolean equations. Both the area and speed performance are considered during the logic optimization process. Experimental results show that the synthesized circuits have better area and/or speed performance compared with those obtained using Synopsys logic synthesis tools.

In this thesis, a novel low power multiplier design is introduced. We utilize the bypassing logic to construct a multiplier based on ripple carry array to minimize the switching activities rather than carry save array for the low power requirement and tree structure to enhance the performance. The advantage of using the bypassing logic in the ripple carry array multiplier is that it can use less extra hardware and achieve more power saving compared with conventional multipliers. The design of our circuit uses the standard TSMC 0.18um technology and simulates with Hspice. According to the simulation results, the proposed design can obtain power saving around 15% more than conventional multipliers, although it must occupy larger area.

The first topic of this thesis is a C-less and R-less ASK (Amplitude Shift Keying) demodulator design for wireless implantable devices. Lots of prior ASK demodulators were composed of one or more capacitors which might be integrated in a chip or positioned off-chip on a PCB (Printed Circuit Board). The capacitor increases the area of the implantable system regardless of on-chip or off-chip, which violates the small-scale requirement for implanted applications. Thus, this work proposes a miniature ASK demodulator without any passive elements, i.e., R or C. The noise margin of the envelope detector in the C-less ASK demodulator is enlarged such that any Schmitt trigger or current limiting resistor is no longer needed. It results in the number of transistors required for the ASK demodulator circuit is reduced to 12. The second topic of this thesis is a design of a low-power 2-dimensional bypassing multiplier. The proposed bypassing cells constituting the multiplier skip redundant signal transitions when the horizontally (row) partial product or the vertically (column) operand is zero. Thorough post-layout simulations show that the power dissipation of the proposed design is reduced by more than 41% compared to the prior design with obscure penalty of delay and area.

Recently, multimedia applications are used widely in many embedded and portable systems, such as mobile phones, MP3 player and PDA, which require lower power consumption within high performance constraints. Therefore, power-efficient design becomes a more important objective in Very Large Scale Integration (VLSI) designs. Moreover, the multiplication unit always lies on the critical path and ultimately determines the performance and power consumption of arithmetic computing systems. To achieve high-performance and lengthen the battery lifetime, it is crucial to develop a multiplier with high-speed and low power consumption. In multimedia and digital signal processing (DSP) applications, many low-power approaches have been presented to lessen the power consumption of multipliers by eliminating spurious computations. Moreover, the multiplication operations adopted in these systems usually allow accuracy loss to output data so as to achieve more power savings. Based on these conceptions, this dissertation considers input data characteristics and the arithmetic features of multiplications in various multimedia and DSP applications and presents novel power reduction and truncation techniques to design power-efficient multipliers and high-accuracy fixed-width multipliers. In the design of array and tree multipliers, we first propose a low power pipelined truncated multiplier which dynamically deactivates non-effective circuitry based on input range. Moreover, the proposed multiplier offers a flexible tradeoff between power reduction and product precision. This reconfigurable characteristic is very useful to systems which have different requirement on output precision. Second, a low-power configurable Booth multiplier that supports several multiplication modes and eliminates the redundant computations of sign bits in multipliers as much as possible is developed. This architecture can efficaciously decrease the power consumption of systems which demand computing performance and flexibility simultaneously. Although these two kinds of low power multipliers can achieve significant power savings, the hardware complexity of error compensation circuits and error performance in terms of the mean error and mean-square error are unsuitable for many multimedia systems composed of a large amount of multiply-accumulate operations. To efficiently improve the accuracy with less hardware complexity, we propose new error compensation circuits for fixed-width tree multipliers and fixed-width modified Booth multipliers. In the design of floating-point multipliers, we propose a low power variable-latency floating-point multiplier which is compliant with IEEE 754-1985 and suitable for 3-D graphics and multimedia applications. In the architecture, the significand multiplier is first partitioned into the upper and lower parts. Next, an efficient prediction scheme for the carry bit, sticky bit, and the upper part of significand product is developed. While the correct prediction occurs, the computation of lower part of significand multiplier is shut down and therefore the floating-point multiplication can consume less power and be completed early. In the design of modular multipliers, we propose an efficient modular multiplication algorithm to devise a high performance and low power modular multiplier. The proposed algorithm adopts the quotient pipelining and superfluous-operation elimination technique to discard the data dependency and redundant computational cycles of radix-2 Montgomery¡¦s multiplication algorithm so that the operation speed, power dissipation, and energy consumption of modular multipliers can be significantly improved.

In many multimedia applications, a little error in the output results is allowable. Therefore, this thesis presents an iterative floating-point multiplier with multiple precision to reduce the energy consumption of floating-point multiplication operations. The multiplier can provide the users with three kinds of modes. The distinction among the three modes is the accepted output error and the achievable energy saving through reducing the length of mantissa in the multiplication operation. In addition, to reduce the area of multiple precision floating-point multiplier we use the iterative structure to implement the mantissa multiplier in a floating point multiplier. Moreover the C++ language is adopted to evaluate the product error between each mode and the IEEE754 single precision multiplier. When the multimedia applications request high precision, the multiple precision floating-point multiplier will iteratively execute the 4-2 compression tree three times and the product error is around 10e-5%. The second-mode with the middle accuracy will iteratively execute the 4-2 compression tree two times and the product error is around 10e-3%. The third mode with the lowest accuracy will execute the 4-2 compression tree once and the product error is around 1%, it requires less execution cycle number. When compared with the tree-stage IEEE754 single-precision multiplier, the proposed iterative floating-point multiplier can save 42.54% area. For IDCT application, it can save 37.78% energy under 1% error constraint, For YUV to RGB application, it can save 31.36% energy under 1.1% error constraint. The experimental results demonstrate that the proposed multiple precision iterative floating-point multiplier can significantly reduce the energy consumption of multimedia applications that allow a little output distortion