ABSTRACT Due to the rapid progress in the field of VLSI, improvements in speed, power and area are quite evident. Research and development in this field are motivated by growing markets of portable mobile devices such as personal multimedia players, cellular phones, digital camcorders and digital cameras. Among the recently popular logic families, pass transistor logic is promising for low power applications as compared to conventional static CMOS because of lower transistor count. This thesis proposes four novel designs for Booth encoder and selector logic using pass logic principles. These new designs are implemented and used to build a 64 x 64-bit multiplier. The proposed Booth encoder and selector logic are competitive with the existing and shows substantial reduction in transistor count. It also shows improvements in delay when compared to two of the three published works.

<p>In comparison to other basic arithmetic operations, such as addition, subtraction and multiplication,division is far more complex and expensive. Many division algorithms, except for lookup tables, rely on recursion with usually complex operations in the loop. Even if the cost in terms of area and computational complexity sometimes can be made low, the latency is usually high anyway, due to the number of iterations required. Therefore, in order to find a faster method and a method that provides better precision, a non-recursive polynomial-based algorithm was developed by the Department of Electrical Engineering at Linköping University. </p><p>After having performed high-level modelling in Matlab, promising results were achieved for up to 32 bits of accuracy. However, since the cost model did not take in account other factors that are important when implementing in hardware, the question remained whether the division algorithm was also competitive in practice or not. Therefore, in order to investigate that, this thesis work was initiated. </p><p>This report describes the hardware implementation, the optimization and the evaluation of this division algorithm, regarding latency and hardware cost for numbers with different precisions. In addition to this algorithm, the common Newton-Raphson algorithm has also been implemented, to serve as a reference.</p>

<p>This thesis discusses the design and implementation of a VHDL generator for Wallace tree with (3:2) counter modules and (2:2) counter modules to solve fast addition problem.</p><p>The basic research has been carried out by MATLAB programming environment and automatic generation of VHDL file based on the result obtained from MATLAB simulation. MODELSIM has been used for compilation and simulation of the VHDL file.</p>

In comparison to other basic arithmetic operations, such as addition, subtraction and multiplication,division is far more complex and expensive. Many division algorithms, except for lookup tables, rely on recursion with usually complex operations in the loop. Even if the cost in terms of area and computational complexity sometimes can be made low, the latency is usually high anyway, due to the number of iterations required. Therefore, in order to find a faster method and a method that provides better precision, a non-recursive polynomial-based algorithm was developed by the Department of Electrical Engineering at Linköping University. After having performed high-level modelling in Matlab, promising results were achieved for up to 32 bits of accuracy. However, since the cost model did not take in account other factors that are important when implementing in hardware, the question remained whether the division algorithm was also competitive in practice or not. Therefore, in order to investigate that, this thesis work was initiated. This report describes the hardware implementation, the optimization and the evaluation of this division algorithm, regarding latency and hardware cost for numbers with different precisions. In addition to this algorithm, the common Newton-Raphson algorithm has also been implemented, to serve as a reference.

This thesis discusses the design and implementation of a VHDL generator for Wallace tree with (3:2) counter modules and (2:2) counter modules to solve fast addition problem. The basic research has been carried out by MATLAB programming environment and automatic generation of VHDL file based on the result obtained from MATLAB simulation. MODELSIM has been used for compilation and simulation of the VHDL file.