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Electronic noise in nanostructures: limitations and sensing applicationsKim, Jong Un 25 April 2007 (has links)
Nanostructures are nanometer scale structures (characteristic length less than 100 nm) such as
nanowires, ultra-small junctions, etc. Since nanostructures are less stable, their characteristic
volume is much smaller compared to defect sizes and their characteristic length is close to
acoustical phonon wavelength. Moreover, because nanostructures include significantly fewer
charge carriers than microscale structures, electronic noise in nanostructures is enhanced
compared to microscale structures. Additionally, in microprocessors, due to the small gate
capacitance and reduced noise margin (due to reduced supply voltage to keep the electrical field
at a reasonable level), the electronic noise results in bit errors. On the other hand, the enhanced
noise is useful for advanced sensing applications which are called fluctuation-enhanced sensing.
In this dissertation, we first survey our earlier results about the limitation of noise posed on
specific nano processors. Here, single electron logic is considered for voltage controlled logic
with thermal excitations and generic shot noise is considered for current-controlled logic.
Secondly, we discuss our recent results on the electronic noise in nanoscale sensors for SEnsing
of Phage-Triggered Ion Cascade (SEPTIC, for instant bacterial detection) and for silicon
nanowires for viral sensing. In the sensing of the phage-triggered ion cascade sensor,
bacteriophage-infected bacteria release potassium ions and move randomly at the same time;
therefore, electronic noise (i.e., stochastic signals) are generated. As an advanced model, the
electrophoretic effect in the SEPTIC sensor is discussed. In the viral sensor, since the
combination of the analyte and a specific receptor located at the surface of the silicon nanowire
occurs randomly in space and time, a stochastic signal is obtained. A mathematical model for a
pH silicon nanowire nanosensor is developed and the size quantization effect in the nanosensor
is also discussed. The calculation results are in excellent agreement with the experimental results
in the literature.
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Etude de la localisation de nanofils de silicium sur des surfaces Si3N4 et SiO2 micro & nanostructurées / Localization of silicon nanowires on micro and nano structured surfaces of Si3N4 & SiO2Chamas, Hassan 25 June 2013 (has links)
Les nanofils de semiconducteurs, d’oxides métalliques ou encore les nanotubes de carbone suscitent beaucoup d’intérêt pour des applications en nanoélectronique, mais également pour le développement de nanocapteurs chimiques ou biologiques. Cet intérêt pour les capteurs est principalement motivé par les propriétés liées aux faibles dimensions radiales et aux forts ratios surface/volume de ces nano-objets qui les rendent extrêmement sensibles aux effets de surface, et par conséquent à leur environnement. Les variations de charges de surface des matériaux en fonction du milieu peuvent également être utilisées comme une voie pour l’auto-organisation de nano-objets. Ce travail s’inscrit dans cette perspective. La voie chimique explorée pour la localisation est compatible avec une intégration de nano-objets a posteriori sur une technologie CMOS silicium. Plus précisément, notre approche « Bottom Up » repose sur les variations de la charge de surface du SiO2 et du Si3N4 en fonction du pH de la solution. Après une revue de littérature sur les points de charge nulle (PZC) des différents isolants selon leurs techniques d’élaboration, nous avons étudié expérimentalement les propriétés de couches de SiO2 thermique et de Si3N4 (LPCVD). Les PZC de ces différents isolants ont été déterminés par des mesures d’impédance électrochimique réalisées sur des structures EIS et couplées avec des mesures d’angle de contact en fonction du pH. Une étude systématique en fonction du pH (1.5 à 4.5) a été réalisée et un protocole expérimental a pu être mis en place pour démontrer la localisation préférentiellement les nanofils de silicium sur Si3N4. Nous avons pu démontrer qu’une localisation quasi parfaite était possible pour un pH compris entre 3 et 3,25 conformément au modèle électrostatique proposé. Le procédé développé présente l’avantage d’être simple, reproductible et peu coûteux. Il utilise une chimie très classique à température ambiante pour localiser des nano-objets silicium sans présenter de risque pour les dispositifs CMOS des niveaux inférieurs. / Semiconductor and metal oxides nanowires as well as carbon nanotubes are attractive for Nano electronic applications but also for chemical or biological sensors. This interest is related to the properties of 1D nanostructures with very small diameters and with high surface / volume ratios. The main property of such nanostructures is the high electrostatic sensitivity to their environment. The related surface charge variations as function of the medium may also be used as a way for the nanostructure self-organization. This work has been developed with this perspective. The investigated chemical approach is compatible with a post-integration of nano-objects on silicon CMOS technologies. More precisely, our “Bottom Up” method uses the different surface charges on SiO2 and Si3N4 as a function of the solution pH. After a literature review focused on the Point of Zero Charge (PZC) for insulating materials depending on the fabrication techniques, we have studied experimentally thermal SiO2 and LPCVD Si3N4 layers grown or deposited on silicon. The PZC of our layers have been determined using electrochemical impedance measurements in a EIS configuration. These impedance measurements have been cross correlated with contact angle measurements as function of the solution’s pH. A systematic study as function of pH in the 1.5 – 4.5 range as been carried out and an experimental protocol has been found in order to demonstrate the preferential localization of silicon nanowires on Si3N4. From this study, it is found that a quasi-perfect localization is possible for a pH between 3 and 3.25 as expected from the proposed electrostatic model. Finally, the developed process is low-cost, simple and reproducible which presents important advantages. It uses a very classical chemistry at ambient temperature and allows the localization of silicon nano-objects without any risk for the CMOS devices of the front-end level.
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