Transistor aging through negative bias temperature instability (NBTI) has become a major lifetime constraint in VLSI circuits. We propose a technique that uses antifuses to widen PMOS transistors later in a circuit?s life cycle to combat aging. Using HSPICE and 70nm BPTM process numbers, we simulated the technique on four circuits (a ring oscillator, a fan-out four circuit, an ISCAS c432 and c2670). Over the lifetime of the circuit, our simulations predict a 8.89% and a 13% improvement in power in the c432 and c2670 circuits respectively when compared to similarly performing traditional circuits.

With the gradual advance of the state-of-the-art VLSI manufacturing technology into the sub-45nm regime, engineering a reliable, high performance VLSI chip with economically attractive yield in accordance with Moore's law of scaling and integration has become extremely difficult. Some of the most serious challenges that make this task difficult are: a) the delay of a transistor is strongly dependent on process induced mechanical stress around it, b) the reliability of devices is affected by several aging mechanisms like Negative Bias Temperature Instability (NBTI), hot carrier injection (HCI), etc and c) the delay and reliability of any device are strongly related to lithographically drawn geometry of various features on wafer. These three challenges are the main focus of this dissertation. High performance fabrication processes routinely use embedded silicon-germanium (eSiGe) technology that imparts compressive mechanical stress to PMOS devices. In this work, cell level timing models considering flexibility to modulate active area to change mechanical stress, were proposed and exploited to perform timing optimization during circuit placement phase. Analysis of key physical synthesis optimization steps such as gate sizing and repeater insertion was done to understand and exploit mechanical stress to significantly improve delay of interconnect and device dominated circuits. Regarding circuit reliability, the proposed work is focused on reducing the clock skew degradation due to NBTI effect specially due to the use of clock gating technique for achieving low power operation. In addition, we also target the detrimental impact of burn-in testing on NBTI. The problem is identified and a runtime technique to reduce clock skew increase was proposed. For designs with predictable clock gating activities, a zero overhead design time technique was proposed to reduce clock skew increase over time. The concept of using minimum degradation input vector during static burn-in testing is proposed to reduce the impact of burn-in testing on parametric yield. Delay and reliability strongly depend on dimension of various features on the wafer such as gate oxide thickness, channel length and contact position. Increased variability of these dimensions can severely restrict ability to analyze or optimize a design considering mechanical stress and circuit reliability. One key technique to control physical variability is to move towards regular fabrics. However, to make implementation on regular fabrics attractive, high quality physical design tools need to be developed. This dissertation proposes a new circuit placement algorithm to place a design on a structured ASIC platform with strict site and clock constraints and excellent overall wirelength. An algorithm for reducing the clock and leakage power dissipation of a structured ASIC by reducing spine usage is then proposed to allow lower power dissipation of designs implemented using structured ASICs. / text

A miniaturização dos transistores do tipo MOS traz consigo um aumento na variabilidade de seus parâmetros elétricos, originaria do processo de fabricação e de efeitos com dependência temporal, como ruídos e degradação (envelhecimento ou aging). Este aumento de variabilidade no nível de dispositivo se converte aos níveis de circuito e sistema como uma perda de confiabilidade ou de desempenho. Neste trabalho são apresentados métodos de simulação de efeitos causados por armadilhas de cargas (charge traps), como o NBTI e o RTS. Tomando como base simuladores elétricos comerciais, foi desenvolvida uma ferramenta capaz de simular a atividade das armadilhas durante uma simulação transiente. Para tanto, foi criado um componente em Verilog-A e um software de controle escrito em Perl. Dessa forma é possível analisar o impacto de traps (armadilhas) no comportamento do circuito considerando variações ambientais como tensões de operação, bem como analisar efeitos de ruído como o RTS e de aging como NBTI. Foram então desenvolvidos estudos de caso em um inversor, em um caminho crítico com cinco níveis lógicos e em uma memória SRAM de 32 bits, onde foi feita uma análise da relação do NBTI com o histórico do sinal de estresse no circuito. Em um segundo momento foi desenvolvido um método de análise do impacto de NBTI em circuitos digitais no nível de sistema, através de simulações de SSTA. Para tal estudo foi caracterizada a biblioteca NCSU FreePDK 45nm da Nangate, considerando o tempo como um corner, e então realizando-se uma simulação de SSTA em três caminhos críticos de diferentes complexidades. A fim de estudar a acuidade obtida nas simulações realizadas no nível do sistema, também foram realizadas simulações com o simulador elétrico desenvolvido e comparados os resultados. Observou-se um aumento na acuidade das simulações no nível do sistema quando complexidade do circuito estudado aumenta. Tal comportamento é explicado através do teorema do limite central. / The downscaling of MOS transistors leads to an increase of the variability of its electrical parameters generated both by fabrication process and by time dependent effects, such as noise and ageing. This increase of the variability at the device level turns into the circuit and systems level as a loss in the reliability or performance. This thesis presents the development of simulation methods for effects caused by traps, such as NBTI and RTS. Combining commercial electrical simulators, an enhanced Verilog-A transistor model and a control software developed in Perl, a simulation tool was created. The tool properly accounts for the activity of traps during transient electrical simulations. This way it is possible to evaluate the impact of traps in the behavior of circuits taking into account environmental variations, like supply voltage fluctuations, and evaluate noise effects like RTS and aging effects like NBTI. Case studies were carried out, considering an inverter, a five stages logic path and a SRAM, where the workload dependency on NBTI was evaluated. The impact of NBTI on combinational circuits on a system level is then evaluated through SSTA simulations. In order to perform this analysis, the Nangate NCSU FreePDK 45nm library was characterized and the circuit's age was considered as a time corner. SSTA simulations were performed in three paths of different complexities and then its results were compared with the results obtained with the electrical simulator developed showing an increase of accuracy of the SSTA method as a function of the circuit's complexity. This behavior is explained by the Central Limit Theorem.

Esta dissertação explora os desafios agravados pela miniaturização da tecnologia na fabricação e projeto de circuitos integrados digitais. Os efeitos físicos do regime nanométrico reduzem o rendimento da produção e encurtam a vida útil dos dispositivos, restringindo a utilidade dos padrões de projeto convencionais e ameaçando a evolução da tecnologia CMOS como um todo. Nesta dissertação é exposta uma consistente revisão bibliográfica dos principais efeitos físicos parasitas presentes no regime nanométrico. Como o NBTI tem recebido destaque na literatura relacionada à confiabilidade de circuitos, este efeito de envelhecimento recebe destaque também neste texto, sendo explorado mais detalhadamente. Diversas técnicas de avaliação de redução do NBTI são demonstradas, sendo apresentados, em cada um destes tópicos, trabalhos desenvolvidos no âmbito desta dissertação e seus resultados. O circuito proposto como técnica de avaliação de NBTI permite uso de simulações elétricas para análise de degradação de circuitos. A análise da influência do rearranjo da estrutura de transistores para reduzir a degradação quanto ao NBTI apresenta bons resultados e não impede o uso de outras técnicas combinadas. / This thesis explores the challenges worsened by the technology miniaturization in fabrication and design of digital integrated circuits. The physical effects of nanometric regime reduce the production yield and shorten the devices lifetime, restricting the usefulness of standard design flows and threatening the evolution of CMOS technologies. This thesis exposes a consistent bibliographic review about the main aggressive physical effects of nanometric regime. NBTI has received special attention in reliability literature, so this text follows the same strategy, deeply exploring this aging effect. A broad set of NBTI evaluation and mitigation techniques are explained, including developed works in each one of these categories. The proposed circuit as NBTI evaluation technique allows the use of electrical simulation for circuit degradation analysis. The analysis of the transistors arrangement restructuring as a technique for NBTI degradation reduction shows satisfactory results, while does not restrict the use of other combined techniques.

A miniaturização dos transistores do tipo MOS traz consigo um aumento na variabilidade de seus parâmetros elétricos, originaria do processo de fabricação e de efeitos com dependência temporal, como ruídos e degradação (envelhecimento ou aging). Este aumento de variabilidade no nível de dispositivo se converte aos níveis de circuito e sistema como uma perda de confiabilidade ou de desempenho. Neste trabalho são apresentados métodos de simulação de efeitos causados por armadilhas de cargas (charge traps), como o NBTI e o RTS. Tomando como base simuladores elétricos comerciais, foi desenvolvida uma ferramenta capaz de simular a atividade das armadilhas durante uma simulação transiente. Para tanto, foi criado um componente em Verilog-A e um software de controle escrito em Perl. Dessa forma é possível analisar o impacto de traps (armadilhas) no comportamento do circuito considerando variações ambientais como tensões de operação, bem como analisar efeitos de ruído como o RTS e de aging como NBTI. Foram então desenvolvidos estudos de caso em um inversor, em um caminho crítico com cinco níveis lógicos e em uma memória SRAM de 32 bits, onde foi feita uma análise da relação do NBTI com o histórico do sinal de estresse no circuito. Em um segundo momento foi desenvolvido um método de análise do impacto de NBTI em circuitos digitais no nível de sistema, através de simulações de SSTA. Para tal estudo foi caracterizada a biblioteca NCSU FreePDK 45nm da Nangate, considerando o tempo como um corner, e então realizando-se uma simulação de SSTA em três caminhos críticos de diferentes complexidades. A fim de estudar a acuidade obtida nas simulações realizadas no nível do sistema, também foram realizadas simulações com o simulador elétrico desenvolvido e comparados os resultados. Observou-se um aumento na acuidade das simulações no nível do sistema quando complexidade do circuito estudado aumenta. Tal comportamento é explicado através do teorema do limite central. / The downscaling of MOS transistors leads to an increase of the variability of its electrical parameters generated both by fabrication process and by time dependent effects, such as noise and ageing. This increase of the variability at the device level turns into the circuit and systems level as a loss in the reliability or performance. This thesis presents the development of simulation methods for effects caused by traps, such as NBTI and RTS. Combining commercial electrical simulators, an enhanced Verilog-A transistor model and a control software developed in Perl, a simulation tool was created. The tool properly accounts for the activity of traps during transient electrical simulations. This way it is possible to evaluate the impact of traps in the behavior of circuits taking into account environmental variations, like supply voltage fluctuations, and evaluate noise effects like RTS and aging effects like NBTI. Case studies were carried out, considering an inverter, a five stages logic path and a SRAM, where the workload dependency on NBTI was evaluated. The impact of NBTI on combinational circuits on a system level is then evaluated through SSTA simulations. In order to perform this analysis, the Nangate NCSU FreePDK 45nm library was characterized and the circuit's age was considered as a time corner. SSTA simulations were performed in three paths of different complexities and then its results were compared with the results obtained with the electrical simulator developed showing an increase of accuracy of the SSTA method as a function of the circuit's complexity. This behavior is explained by the Central Limit Theorem.

Esta dissertação explora os desafios agravados pela miniaturização da tecnologia na fabricação e projeto de circuitos integrados digitais. Os efeitos físicos do regime nanométrico reduzem o rendimento da produção e encurtam a vida útil dos dispositivos, restringindo a utilidade dos padrões de projeto convencionais e ameaçando a evolução da tecnologia CMOS como um todo. Nesta dissertação é exposta uma consistente revisão bibliográfica dos principais efeitos físicos parasitas presentes no regime nanométrico. Como o NBTI tem recebido destaque na literatura relacionada à confiabilidade de circuitos, este efeito de envelhecimento recebe destaque também neste texto, sendo explorado mais detalhadamente. Diversas técnicas de avaliação de redução do NBTI são demonstradas, sendo apresentados, em cada um destes tópicos, trabalhos desenvolvidos no âmbito desta dissertação e seus resultados. O circuito proposto como técnica de avaliação de NBTI permite uso de simulações elétricas para análise de degradação de circuitos. A análise da influência do rearranjo da estrutura de transistores para reduzir a degradação quanto ao NBTI apresenta bons resultados e não impede o uso de outras técnicas combinadas. / This thesis explores the challenges worsened by the technology miniaturization in fabrication and design of digital integrated circuits. The physical effects of nanometric regime reduce the production yield and shorten the devices lifetime, restricting the usefulness of standard design flows and threatening the evolution of CMOS technologies. This thesis exposes a consistent bibliographic review about the main aggressive physical effects of nanometric regime. NBTI has received special attention in reliability literature, so this text follows the same strategy, deeply exploring this aging effect. A broad set of NBTI evaluation and mitigation techniques are explained, including developed works in each one of these categories. The proposed circuit as NBTI evaluation technique allows the use of electrical simulation for circuit degradation analysis. The analysis of the transistors arrangement restructuring as a technique for NBTI degradation reduction shows satisfactory results, while does not restrict the use of other combined techniques.

A miniaturização dos transistores do tipo MOS traz consigo um aumento na variabilidade de seus parâmetros elétricos, originaria do processo de fabricação e de efeitos com dependência temporal, como ruídos e degradação (envelhecimento ou aging). Este aumento de variabilidade no nível de dispositivo se converte aos níveis de circuito e sistema como uma perda de confiabilidade ou de desempenho. Neste trabalho são apresentados métodos de simulação de efeitos causados por armadilhas de cargas (charge traps), como o NBTI e o RTS. Tomando como base simuladores elétricos comerciais, foi desenvolvida uma ferramenta capaz de simular a atividade das armadilhas durante uma simulação transiente. Para tanto, foi criado um componente em Verilog-A e um software de controle escrito em Perl. Dessa forma é possível analisar o impacto de traps (armadilhas) no comportamento do circuito considerando variações ambientais como tensões de operação, bem como analisar efeitos de ruído como o RTS e de aging como NBTI. Foram então desenvolvidos estudos de caso em um inversor, em um caminho crítico com cinco níveis lógicos e em uma memória SRAM de 32 bits, onde foi feita uma análise da relação do NBTI com o histórico do sinal de estresse no circuito. Em um segundo momento foi desenvolvido um método de análise do impacto de NBTI em circuitos digitais no nível de sistema, através de simulações de SSTA. Para tal estudo foi caracterizada a biblioteca NCSU FreePDK 45nm da Nangate, considerando o tempo como um corner, e então realizando-se uma simulação de SSTA em três caminhos críticos de diferentes complexidades. A fim de estudar a acuidade obtida nas simulações realizadas no nível do sistema, também foram realizadas simulações com o simulador elétrico desenvolvido e comparados os resultados. Observou-se um aumento na acuidade das simulações no nível do sistema quando complexidade do circuito estudado aumenta. Tal comportamento é explicado através do teorema do limite central. / The downscaling of MOS transistors leads to an increase of the variability of its electrical parameters generated both by fabrication process and by time dependent effects, such as noise and ageing. This increase of the variability at the device level turns into the circuit and systems level as a loss in the reliability or performance. This thesis presents the development of simulation methods for effects caused by traps, such as NBTI and RTS. Combining commercial electrical simulators, an enhanced Verilog-A transistor model and a control software developed in Perl, a simulation tool was created. The tool properly accounts for the activity of traps during transient electrical simulations. This way it is possible to evaluate the impact of traps in the behavior of circuits taking into account environmental variations, like supply voltage fluctuations, and evaluate noise effects like RTS and aging effects like NBTI. Case studies were carried out, considering an inverter, a five stages logic path and a SRAM, where the workload dependency on NBTI was evaluated. The impact of NBTI on combinational circuits on a system level is then evaluated through SSTA simulations. In order to perform this analysis, the Nangate NCSU FreePDK 45nm library was characterized and the circuit's age was considered as a time corner. SSTA simulations were performed in three paths of different complexities and then its results were compared with the results obtained with the electrical simulator developed showing an increase of accuracy of the SSTA method as a function of the circuit's complexity. This behavior is explained by the Central Limit Theorem.

According to non-stopable progress in wireless communications, it is desirable to integrate the RF front-end with the baseband building blocks of communication circuits into a one chip in the recent years. The CMOS technology advances, this is the reason why it becomes attractive for system-on-a-chip implementation, but CMOS device is getting shrink, so the channel electric field increasing and the hot carrier (HCI) effect becomes more significant. If the oxide is scaled down to less than 3 nm, then there is the possibility of soft or hard oxide breakdown (S/HBD) often takes place. As a result of the oxide trapping and interface generation is the long term performance drift and related reliability problems in devices and circuits. During the scaling and increasing chip power dissipation operating temperatures for device have also is increasing. Another reliability concern is the negative bias temperature instability (NBTI) caused by the interface traps under high temperature and negative gate voltage bias are arising while the operation temperature of devices is increasing. Parameter’s extraction is a very important part of the current electronic components modeling process, as it looking for the value of the unknown parameters in mathematical model, which represents physical behavior of given electronic component. The problem of parameter extraction is that fits electronic components mathematical model to a measured data set is an ill-posed problem and its solution is inherently difficult. This diploma thesis presents the parameter extraction, optimization methodology and verifies it on a case study of a MOSFET mathematical models (LEVEL1, LEVEL2 and LEVEL3) parameter extraction. The presented nonlinear method is based on the method of the least squares, which is solved with the aid of Levenberg- Marquardt’s algorithm.

Global warming and air pollution are the major problems facing the world today. Therefore strict environmental legislation on the emission of harmful gases from motor vehicles has forced the automobile industry to search for alternative materials or new materials for exhaust systems. In order to produce cleaner exhaust gases, the exhaust temperature needs to be increased to approximately 900oC. Therefore, exhaust manifolds are exposed repeatedly to hot gases as they are nearest to the engine requiring good oxidation resistance, thermal fatigue properties, cold workability and weldability. One such material to meet the above characteristics is AISI 441 ferritic stainless steel, a dual stabilised Ti and Nb ferritic stainless steel. Ti and Nb are added to stainless steel to stabilise C and N due to their high tendency to form carbonitrides (Ti,Nb)(C,N) and laves phase (Fe2Nb) and Fe3Nb3C. With 18% Cr content, this steel has a good corrosion resistance at elevated temperatures. Included in many applications of this steel are those requiring deep drawing and related forming operations. However, the drawability and stretchability of ferritic stainless steels is inferior to that of the more expensive austenitic stainless steels. For instance, Columbus Stainless has experienced ridging/roping problems at times during the manufacturing process of type AISI 441 ferritic stainless steel. It is believed that this problem is related to crystallographic texture of materials which have effect on formability. The R-value in FSS can be improved through optimisation of chemical composition, which includes reducing the carbon content, and processing conditions such as reducing the slab reheating temperature, increasing annealing temperature and refining the hot band grain size. Therefore the aim of this research project was firstly to investigate effect of amount of cold reduction and annealing temperature on texture evolution and its influence on formability. The as received 4.5 mm hot band steel was cold rolled by 62, 78 and 82% reductions respectively followed by isothermal annealing of each at 900oC, 950oC and 1025oC for 3 minutes. Orientation distribution function (ODF) through X-ray diffractometer (XRD) measurement was used to characterise the crystallographic texture formed in the steel using PANanalytical X’Pert PRO diffractrometer with X’celerator detector and variable divergence. Microstructures were characterised using optical microscopy and scanning electron microscope (SEM). The results show that steels that received 78% cold reduction and annealed at 1025oC recorded the highest Rm-value and lowest ΔR-value which enhances its deep drawing capability. In addition, this steel showed the highest intensity of shifted γ-fibre, notably {554}<225> and {334}<483>. It can therefore be concluded that the γ-fibre which favours deep drawing, is optimal after 78% cold reduction and annealing at 1025oC. The second objective was to investigate the effect of (Nb+Ti) content on the crystallographic texture and the subsequent formability and ridging severity. AISI 441 ferritic stainless steel with different amount of (Nb+Ti) content was used i.e. Steel A (0.26Nb+0.2Ti), Steel B (0.44Nb+0.15Ti) and steel C (0.7Nb+0.32Ti). After a strain of 10%, steels A exhibited the least resistance against surface ridging with average roughness Ra of 1.5 μm followed by steels B with an average roughness Ra of 1.1μm. Steel C showed the highest resistance to ridging with an average roughness Ra of 0.64 μm. This was attributed to the increase in carbonitrites (NbTi)(C,N) due to increased (Nb+Ti) content which acted as nucleation sites for γ-fibre. / Dissertation (MEng)--University of Pretoria, 2013. / gm2014 / Materials Science and Metallurgical Engineering / unrestricted

The continued scaling of transistors has led to an exponential increase in on-chip power density, which has resulted in increasing temperature. In turn, the increase in temperature directly leads to the increase in the rate of wear of a processor. Negative-bias temperature instability (NBTI) is one of the most dominant integrated circuit (IC) failure mechanisms [13, 5] that strongly depends on temperature. NBTI manifests in the form of increased circuit delays which can lead to timing failures and processor crashes. The ability to monitor the wear progression of a processor due to NBTI is valuable when designing real-time embedded systems. While NBTI can be detected using wear state sensors, not all chips are equipped with these sensors because detecting wear due to NBTI requires modifications to the chip design and incurs area and power overhead. NBTI sensor data may also not be exposed to users in software. In addition, wear sensors cannot take into account variations in wear due to the differences in the wear sensor devices and the other functional devices and their operating conditions. In this paper, we propose a lightweight, online methodology to monitor the wear process due to NBTI for off-the-shelf embedded processors. Our proposed method requires neither data on the threshold voltage and critical paths nor additional hardware. Our methodology can also be extended to predict the wear progression due to some other dominant IC failure mechanisms. Experiments on embedded processors provide insights on NBTI wear progression over time. This knowledge can be used to design real-time embedded systems that explicitly consider runtime wear progression to increase predictability and maintain lifetime reliability requirements.