Simultaneous recordings of single and multi-unit neural signals from multiple cortical areas in the brain are a vital tool for gaining more understanding of the operating mechanism of the brain as well as for developing Brain Machine Interfaces. Monitoring the activity levels of hundreds or even thousands of neurons can lead to reliable decoding of brain signals for controlling prosthesis of multiple degrees of freedom and different functionalities. With the advancement of high density microelectrode arrays, the craving of neuroscience research to record the activity of thousands of neurons is achievable. Recently CMOS-based Micro-electrode Arrays MEAs featuring high spatial and temporal resolution have been reported. The augmentation in the number of recording sites carries different challenges to the neural signal processing system. The primary challenge is the massive increase in the incoming data that needs to be transmitted and processed in real time. Data reduction based on the sparse nature of the neural signals with respect to time becomes essential. The dissertation presents the design of a neural spike-based data reduction platform that can handle a few thousands of channels on Field Programmable Gate Arrays (FPGAs), making use of their massive parallel processing capabilities and reconfigurability. For Standalone implementation the spike detector core uses Finite State Machines (FSMs) to control the interface with the data acquisition as well as sending the spike waveforms to a common output FIFO. The designed neural signal processing platform integrates the application of high-speed serial Multi-Gigabit transceivers on FPGAs to allow massive data transmission in real time. It also provides a design for autonomous threshold setting for each channel. / Electrical and Computer Engineering

Brain Computer Interfaces (BCI) are devices that translate acquired neural signals to command and control signals. Applications of BCI include neural rehabilitation and neural prosthesis (thought controlled wheelchair, thought controlled speller etc.) to aid patients with disabilities and to augment human computer interaction. A successful practical BCI requires a faithful acquisition modality to record high quality neural signals; a signal processing system to construct appropriate features from these signals; and an algorithm to translate these features to appropriate outputs. Intracortical recordings like local field potentials provide reliable high SNR signals over long periods and suit BCI applications well. However, the non-stationarity of neural signals poses a challenge in robust decoding of subject behavior. Most BCI research focuses either on developing daily re-calibrated decoders that require exhaustive training sessions; or on providing cross-validation results. Such results ignore the variation of signal characteristics over different sessions and provide an optimistic estimate of BCI performance. Specifically, traditional BCI algorithms fail to perform at the same level on chronological data recordings. Neural signals are susceptible to variations in signal characteristics due to changes in subject behavior and learning, and variability in electrode characteristics due to tissue interactions. While training day-specific BCI overcomes signal variability, BCI re-training causes user frustration and exhaustion. This dissertation presents contributions to solve these challenges in BCI research. Specifically, we developed decoders trained on a single recording session and applied them on subsequently recorded sessions. This strategy evaluates BCI in a practical scenario with a potential to alleviate BCI user frustration without compromising performance. The initial part of the dissertation investigates extracting features that remain robust to changes in neural signal over several days of recordings. It presents a qualitative feature extraction technique based on ranking the instantaneous power of multichannel data. These qualitative features remain robust to outliers and changes in the baseline of neural recordings, while extracting discriminative information. These features form the foundation in developing robust decoders. Next, this dissertation presents a novel algorithm based on the hypothesis that multiple neural spatial patterns describe the variation in behavior. The presented algorithm outperforms the traditional methods in decoding over chronological recordings. Adapting such a decoder over multiple recording sessions (over 6 weeks) provided > 90% accuracy in decoding eight movement directions. In comparison, performance of traditional algorithms like Common Spatial Patterns deteriorates to 16% over the same time. Over time, adaptation reinforces some spatial patterns while diminishing others. Characterizing these spatial patterns reduces model complexity without user input, while retaining the same accuracy levels. Lastly, this dissertation provides an algorithm that overcomes the variation in recording quality. Chronic electrode implantation causes changes in signal-to-noise ratio (SNR) of neural signals. Thus, some signals and their corresponding features available during training become unavailable during testing and vice-versa. The proposed algorithm uses prior knowledge on spatial pattern evolution to estimate unknown neural features. This algorithm overcomes SNR variations and provides up to 93% decoding of eight movement directions over 6 weeks. Since model training requires only one session, this strategy reduces user frustration. In a practical closed-loop BCI, the user learns to produce stable spatial patterns, which improves performance of the proposed algorithms. / text

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No / An area-efficient hardware architecture is used to map fully parallel cortical columns on Field Programmable Gate Arrays (FPGA) is presented in this paper. To demonstrate the concept of this work, the proposed architecture is shown at the system level and benchmarked with image and speech recognition applications. Due to the spatio-temporal nature of spiking neurons, this has allowed such architectures to map on FPGAs in which communication can be performed through the use of spikes and signal can be represented in binary form. The process and viability of designing and implementing the multiple recurrent neural reservoirs with a novel multiplier-less reconfigurable architectures is described.

Decoding algorithms for brain machine interfaces map neural firing times to the underlying biological output signal through dynamic tuning functions. In order to maintain an accurate estimate of the biological signal, the state of the tuning function parameters must be tracked simultaneously. The evolution of this system state is often estimated by an adaptive filter. Recent work demonstrates that the Bayesian auxiliary particle filter (BAPF) offers improved estimates of the system state and underlying output signal over existing techniques. Performance of the BAPF is evaluated under both ideal conditions and commonly encountered spike detection errors such as missed and false detections and missorted spikes. However, this increase in neuronal signal decoding accuracy is at the expense of an increase in computational complexity. Real-time execution of the BAPF algorithm for neural signals using a sequential processor becomes prohibitive as the number of particles and neurons in the obs / Electrical and Computer Engineering

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Analyzing the brain's behavior in terms of its neuronal activity is the fundamental purpose of Brain-Machine Interfaces (BMIs). Neuronal activity is often assumed to be encoded in the rate of neuronal action potential spikes. Successful performance of a BMI system is tied to the efficiency of its individual processing elements such as spike detection, sorting and decoding. To achieve reliable operation, BMIs are equipped with hundreds of electrodes at the neural interface. While a single electrode/tetrode communicates with up to four neurons at a given instant of time, a typical interface communicates with an ensemble of hundreds or even thousands of neurons. However, translation of these signals (data) into usable information for real-time BMIs is bottlenecked due to the lack of efficient real-time algorithms and real-time hardware that can handle massively parallel channels of neural data. The research presented here addresses this issue by developing real-time neural processing algorithms that can be implemented in reconfigurable hardware and thus, can be scaled to handle thousands of channels in parallel. The developed reconfigurable system serves as an evaluation platform for investigating the fundamental design tradeoffs in allocating finite hardware resources for a reliable BMI. In this work, the generic architectural layout needed to process neural signals in a massive scale is discussed. A System-on-Chip design with embedded system architecture is presented for FPGA hardware realization that features (a) scalability (b) reconfigurability, and (c) real-time operability. A prototype design incorporating a dual processor system and essential neural signal processing routines such as real-time spike detection and sorting is presented. Two kinds of spike detectors, a simple threshold-based and non-linear energy operator-based, were implemented. To achieve real-time spike sorting, a fuzzy logic-based spike sorter was developed and synthesized in the hardware. Furthermore, a real-time kernel to monitor the high-level interactions of the system was implemented. The entire system was realized in a platform FPGA (Xilinx Virtex-5 LX110T). The system was tested using extracellular neural recordings from three different animals, a owl monkey, a macaque and a rat. Operational performance of the system is demonstrated for a 300 channel neural interface. Scaling the system to 900 channels is trivial. / Electrical and Computer Engineering

Indiana University-Purdue University Indianapolis (IUPUI) / Neural signal processing to decode neural activity has been an active research area in the last few decades. The next generation of advanced multi-electrode neuroprosthetic devices aim to detect a multiplicity of channels from multiple electrodes, making the relatively time-critical processing problem massively parallel and pushing the computational demands beyond the limits of current embedded digital signal processing (DSP) techniques. To overcome these limitations, a new hybrid computational technique was explored, the Extended Analog Computer (EAC). The EAC is a digitally confgurable analog computer that takes advantage of the intrinsic ability of manifolds to solve partial diferential equations (PDEs). They are extremely fast, require little power, and have great potential for mobile computing applications. In this thesis, the EAC architecture and the mechanism of the formation of potential/current manifolds was derived and analyzed to capture its theoretical mode of operation. A new mode of operation, resistance mode, was developed and a method was devised to sample temporal data and allow their use on the EAC. The method was validated by demonstration of the device solving linear diferential equations and linear functions, and implementing arbitrary finite impulse response (FIR) and infinite impulse response (IIR) linear flters. These results were compared to conventional DSP results. A practical application to the neural computing task was further demonstrated by implementing a matched filter with the EAC simulator and the physical prototype to detect single fiber action potential from multiunit data streams derived from recorded raw electroneurograms. Exclusion error (type 1 error) and inclusion error (type 2 error) were calculated to evaluate the detection rate of the matched filter implemented on the EAC. The detection rates were found to be statistically equivalent to that from DSP simulations with exclusion and inclusion errors at 0% and 1%, respectively.

Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and to elucidate human neurophysiology. The advent of multi-channel micro-electrode arrays has driven the need for electronic store cord neural signals from many neurons. The continuous increase in demand of data from more number of neurons is challenging for the design of an efficient neural recording frontend(NRFE). Power consumption per channel and data rate minimization are two key problems which need to be addressed by next generation of neural recording systems. Area consumption per channel must be low for small implant size. Dynamic range in NRFE can vary with time due to change in electrode-neuron distance or background noise which demands adaptability. In this thesis, techniques to reduce power-per-channel and area-per-channel in a NRFE, via new circuits and architectures, are proposed. An area efficient low power neural LNA is presented in UMC 0.13 μm 1P8M CMOS technology. The amplifier can be biased adaptively from 200 nA to 2 μA , modulating input referred noise from 9.92 μV to 3.9μV . We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier. It obviates the need of large input coupling capacitance in the amplifier which saves considerable amount of chip area. In vitro experiments were performed to validate the applicability of the neural LNA in neural recording systems. ADC is another important block in a NRFE. An 8-bit SAR ADC along with the input and reference buffer is implemented in 0.13 μm CMOS technology. The use of ping-pong input sampling is emphasized for multichannel input to alleviate the bandwidth requirement of the input buffer. To reduce the output data rate, the A/D process is only enabled through a proposed activity dependent A/D scheme which ensures that the background noise is not processed. Based on the dynamic range requirement, the ADC resolution is adjusted from 8 to 1 bit at 1 bit step to reduce power consumption linearly. The ADC consumes 8.8 μW from1Vsupply at1MS/s and achieves ENOB of 7.7 bit. The ADC achieves FoM of 42.3 fJ/conversion in 0.13 μm CMOS technology. Power consumption in SARADCs is greatly benefited by CMOS scaling due to its highly digital nature. However the power consumption in the capacitive DAC does not scale as well as the digital logic. In this thesis, two energy-efficient DAC switching techniques, Flip DAC and Quaternary capacitor switching, are proposed to reduce their energy consumption. Using these techniques, the energy consumption in the DAC can be reduced by 37 % and 42.5 % compared to the present state-of-the-art. A novel concept of code-independent energy consumption is introduced and emphasized. It mitigates energy consumption degradation with small input signal dynamic range.