Målet med examensarbetet är att implementera en mjuk CPU i en FPGA-krets som finns tillgänglig på ett ALTERA DE2 Board. Denna mjuka processor integreras i ett projekt skapat i utvecklingsmiljön Quartus II. Den kommunicera med programmerad logik i FPGA:n och den signalbehandlar en audiosignal (stereo), så att ett eko kan genereras och att volym och balans blir justerbar. Detta styrs av ett tangentbord som kopplas till DE2-kortet och de olika förändringarna på utsignalen visas på en LCD. / The ambition with this thesis is to implement a soft CPU i a FPGA-circuit which is available on an ALTERA DE2 Board. This soft processor is integrated in a project designed in the development environment: Quartus II CAD System. It communicates with programmed logic in the FPGA and it alters an audiosignal so that an eco is generated and so that volume and balance can be adjusted. This is controled from a keyboard which is connected to the DE2-card and all the different adjustments of the outsignal are shown on an LCD.

Technological development has significantly reduced the distance between the performance of systems designed using reconfigurable computing and dedicated hardware. The main sources of performance are the high density level of the FPGAs and the resources? improvement offered by manufacturers, who make more its use more attractive in a variety of applications, emphatically in systems that demand a high degree of flexibility. In this context, the objective of this work consists on the exploration of the resources offered by FPGAs for the development of a multiprocessed platform with the purpose of parallel execution of tasks. In this way, the eCos operating system was modified, with the addition of new characteristics to support of the Symmetric Multiprocessing model, using three soft-Core Altera Nios II processors. On this operating system, all parallelism is directly related to execution of the threads. This platform was analyzed and validated through the execution of parallel algorithms, emphasizing aspects of performance and flexibility compared to other architectures. This work contributes for reaching better results in the execution of tasks in robotics area, which belongs to a domain that demand great competition of tasks, mainly in modules that involve interaction with the external environment / Technological development has significantly reduced the distance between the performance of systems designed using reconfigurable computing and dedicated hardware. The main sources of performance are the high density level of the FPGAs and the resources? improvement offered by manufacturers, who make more its use more attractive in a variety of applications, emphatically in systems that demand a high degree of flexibility. In this context, the objective of this work consists on the exploration of the resources offered by FPGAs for the development of a multiprocessed platform with the purpose of parallel execution of tasks. In this way, the eCos operating system was modified, with the addition of new characteristics to support of the Symmetric Multiprocessing model, using three soft-Core Altera Nios II processors. On this operating system, all parallelism is directly related to execution of the threads. This platform was analyzed and validated through the execution of parallel algorithms, emphasizing aspects of performance and flexibility compared to other architectures. This work contributes for reaching better results in the execution of tasks in robotics area, which belongs to a domain that demand great competition of tasks, mainly in modules that involve interaction with the external environment

O cálculo dos vetores de movimento é utilizado em vários processos na área de visão computacional. Problemas como estabelecer rotas de colisão e movimentação da câmera (egomotion) utilizam os vetores como entrada de algoritmos complexos e que demandam muitos recursos computacionais e consequentemente um consumo maior de energia. O fluxo ótico é uma aproximação do campo gerado pelos vetores de movimento. Porém, para aplicações móveis e de baixo consumo de energia se torna inviável o uso de computadores de uso geral. Um sistema embarcado é definido como um computador desenvolvido com um propósito específico referente à aplicação na qual está inserido. O objetivo principal deste trabalho foi elaborar um módulo em sistema embarcado que realiza o cálculo do fluxo ótico. Foi elaborado um co-projeto de hardware e software dedicado e implementados em FPGAs Cyclone II e Stratix IV para a prototipação do sistema. Desta forma, a implementação de um projeto que auxilia a detecção e medição do movimento é importante não só como aplicação isolada, mas para servir de base no desenvolvimento de outras aplicações como tracking, compressão de vídeos, predição de colisão, etc / The motion vectors calculation is used in many processes in the area of computer vision. Problems such as establishing collision routes and the movement of the camera (egomotion) use this vectors as input for complexes algorithms that require many computational and energy resources. The optical flow is an approximation of the field generated by the motion vectors. However, for mobile, low power consumption applications becomes infeasible to use general-purpose computers. An embedded system is defined as a computer designed with a specific purpose related to the application in which it is inserted. The main objective of this work is to implement a hardware and software co-design to assist the optical flow field calculation using the CycloneII and Stratix IV FPGAs. Sad that, it is easily to see that the implementation of a project to help the detection and measurement of the movement can be the base to the development of others applications like tracking, video compression and collision detection

Technological development has significantly reduced the distance between the performance of systems designed using reconfigurable computing and dedicated hardware. The main sources of performance are the high density level of the FPGAs and the resources? improvement offered by manufacturers, who make more its use more attractive in a variety of applications, emphatically in systems that demand a high degree of flexibility. In this context, the objective of this work consists on the exploration of the resources offered by FPGAs for the development of a multiprocessed platform with the purpose of parallel execution of tasks. In this way, the eCos operating system was modified, with the addition of new characteristics to support of the Symmetric Multiprocessing model, using three soft-Core Altera Nios II processors. On this operating system, all parallelism is directly related to execution of the threads. This platform was analyzed and validated through the execution of parallel algorithms, emphasizing aspects of performance and flexibility compared to other architectures. This work contributes for reaching better results in the execution of tasks in robotics area, which belongs to a domain that demand great competition of tasks, mainly in modules that involve interaction with the external environment / Technological development has significantly reduced the distance between the performance of systems designed using reconfigurable computing and dedicated hardware. The main sources of performance are the high density level of the FPGAs and the resources? improvement offered by manufacturers, who make more its use more attractive in a variety of applications, emphatically in systems that demand a high degree of flexibility. In this context, the objective of this work consists on the exploration of the resources offered by FPGAs for the development of a multiprocessed platform with the purpose of parallel execution of tasks. In this way, the eCos operating system was modified, with the addition of new characteristics to support of the Symmetric Multiprocessing model, using three soft-Core Altera Nios II processors. On this operating system, all parallelism is directly related to execution of the threads. This platform was analyzed and validated through the execution of parallel algorithms, emphasizing aspects of performance and flexibility compared to other architectures. This work contributes for reaching better results in the execution of tasks in robotics area, which belongs to a domain that demand great competition of tasks, mainly in modules that involve interaction with the external environment

O cálculo dos vetores de movimento é utilizado em vários processos na área de visão computacional. Problemas como estabelecer rotas de colisão e movimentação da câmera (egomotion) utilizam os vetores como entrada de algoritmos complexos e que demandam muitos recursos computacionais e consequentemente um consumo maior de energia. O fluxo ótico é uma aproximação do campo gerado pelos vetores de movimento. Porém, para aplicações móveis e de baixo consumo de energia se torna inviável o uso de computadores de uso geral. Um sistema embarcado é definido como um computador desenvolvido com um propósito específico referente à aplicação na qual está inserido. O objetivo principal deste trabalho foi elaborar um módulo em sistema embarcado que realiza o cálculo do fluxo ótico. Foi elaborado um co-projeto de hardware e software dedicado e implementados em FPGAs Cyclone II e Stratix IV para a prototipação do sistema. Desta forma, a implementação de um projeto que auxilia a detecção e medição do movimento é importante não só como aplicação isolada, mas para servir de base no desenvolvimento de outras aplicações como tracking, compressão de vídeos, predição de colisão, etc / The motion vectors calculation is used in many processes in the area of computer vision. Problems such as establishing collision routes and the movement of the camera (egomotion) use this vectors as input for complexes algorithms that require many computational and energy resources. The optical flow is an approximation of the field generated by the motion vectors. However, for mobile, low power consumption applications becomes infeasible to use general-purpose computers. An embedded system is defined as a computer designed with a specific purpose related to the application in which it is inserted. The main objective of this work is to implement a hardware and software co-design to assist the optical flow field calculation using the CycloneII and Stratix IV FPGAs. Sad that, it is easily to see that the implementation of a project to help the detection and measurement of the movement can be the base to the development of others applications like tracking, video compression and collision detection

The widespread use of navigation devices is increasing rapidly. This all becomes possible mainly due to increased development of hardware, for instance increased computing power (e.g. microcontroller, GPS, Compass) and software. The Handheld Navigation (HNS) is one of the navigation techniques. It is used in different fields. Just like any-other means of navigation, it is used to determine the position and direction of the user accurately and find the shortest track with precision. Global Positioning System (GPS) is a technology that can be used to determine position coordinates, time, speed and course over ground. The electronic compass is a traditional device that is used to determine the current directional angle of the user. The goal of the thesis is to compare the results of directions angle and distance from two designs (direction’s angle and distance are calculated based upon information from GPS receiver and the other direction’s angle and distance are calculated based upon information from GPS receiver and Compass). In the thesis, we have developed dual designs to achieve the goal of the thesis. The first design uses the GPS receiver coordinates to calculate the direction angle and distance, the second design integrates the GPS positioning and the digital compass, to calculate the direction and distance of Handheld Navigation user. Each device communicates with the microcontroller through the interfaces. As there are two designs. Directional results are obtained from each design. Then these results are compared with each other. After comparison, the more accurate result is chosen for the user. A Handheld Navigation PCB board design has been made. In addition SD card and LCD display are used. Both designs have been carried out on Altera Cyclone II FPGAs. The result of the prototyping shows, that the best design for Handheld Navigation System is the design that consists of GPS and Compass because the compass sensing is stable depending on the magnetic north while the previous design depends on calculated direction on movement and then also on the speed of movement. / Handhållna navigationssystem för satellitnavigering, GPS, har blivit allt vanligare. Vid navigation måste man känna till riktningen till målet men också i vilken riktning navigationsutrustningen pekar eftersom detta utgör referens för att beräkna korrigeringar. Om navigationsutrustningen rör sig med en viss hastighet så kan rörelseriktningen beräknas från ett antal på varandra följande positions- koordinater. Denna metod fungerar bra i t.ex. ett fordon som rör sig med en rimlig hastighet. Om systemet skall användas av en person som går så uppstår problem. Personen kan stanna upp och vrida runt i olika riktningar. Då finns då inga bra tidigare koordinater för att beräkna rörelseriktningen dvs. hur navigationssystemet pekar. När personen sedan rör sig i en viss riktning så måste systemet förflyttas en viss sträcka innan riktningen kan beräknas. Längden på den sträcka som krävs påverkas också av noggrannheten hos koordinatbestämningen. GPS- systemet har en icke försumbar osäkerhet på ett antal meter. Om en elektronisk kompass används för att bestämma hur navigationssystemet pekar så försvinner kravet på att systemet måste förflyttas för att kunna bestämma sin riktning. I detta examensarbete har ett GPS baserat navigationssystem utvecklats för att kunna jämföra system baserade på enbart GPS med sådana som har också en elektronisk kompass. Ett utvecklingskort för programmerbar logik har använts som plattform. Kortets FPGA-krets innehåller både processor, Nios-II soft core, och interface mot givare och minnen. Resultaten från testerna visar, inte helt oväntat, att ett system med kompass ger en säkrare navigation och en kortare väg mellan start och mål. Detta gäller främst när det finns hinder i vägen.

No description available.

A tendência de integração de diversos componentes em um único chip tem proporcionado um aumento da complexidade dos sistemas computacionais. Tanto as indústrias quanto o meio acadêmico estão em busca de técnicas que possibilitem diminuir o tempo e o esforço gastos com a verificação no processo de desenvolvimento de hardware, a fim de garantir qualidade, robustez e confiabilidade a esses dispositivos. De forma a contribuir para várias aplicações envolvendo a verificação de sistemas, tais como busca por erros de projeto, avaliação de desempenho, otimização de algoritmos e extração de dados do sistema, o presente trabalho propõe um sistema de monitoramento baseado em computação reconfigurável, capaz de observar de forma não intrusiva o comportamento de um SoC (System-on-Chip) em tempo de execução. Tal sistema é composto por um módulo de monitoramento responsável por captar informações de execução de software em um processador embarcado e uma ferramenta de análise, chamada ACAD, que interpreta esses dados. Por meio da realização de experimentos, verificou-se que o sistema desenvolvido foi capaz de fornecer dados fiéis sobre a quantidade de acessos a memória ou a outros periféricos, tempos de execução de porções (ou a totalidade) do código e número de vezes que cada instrução foi executada. Esses resultados permitem traçar, de maneira precisa, o comportamento de um software executado no processador softcore Nios II, contribuindo assim para facilitar o processo de verificação em sistemas baseados em computação reconfigurável / The trend of integrating several components on a single chip has motivated an increase in the complexity of computing systems. Both industry and academy are in search of new techniques that allow time and effort spent with verification on hardware development process to be reduced to guarantee quality, robustness, reability to these devices. In order to contribute to applications in the system verification area, such as search for design errors, performance evaluation, algorithm optimization and data extraction from the system, this work proposes a monitoring system based on reconfigurable computing. This system must be able to have a run-time non-intrusive probing of a System-on-Chip behaviour. It is formed by a monitoring core responsible for capturing software execution information of a embedded processor and an analysis tool, called ACAD, that decodes the data. Empirically, the implemented system was able to provide precise data about the amount of memory and other peripherals accesses, time measurement for sections (or the entire) of the source code, and number of times each instruction was executed. These results allow to draw, in accurate way, the behaviour of a software executed on the softcore Nios II processor, collaborating to make the verification process of systems based on reconfigurable computing easier

Este projeto apresenta uma metodologia aplicada à análise da viabilidade de se otimizar código fonte C para o processador embarcado Nios II. Esta metodologia utiliza ferramentas de análise de código que traçam o perfil da aplicação, identificando suas partes críticas em relação ao tempo de execução, as quais são o gprof e o performance counter. Para otimizar o código para o processador Nios II, são utilizadas tanto instruções customizadas quanto uma ferramenta automática de aceleração de código, o compilador C2H. Como casos de estudo, foram escolhidos três algoritmos devido à sua importância no campo da robótica móvel, sendo eles o gaxpy, o EKF e o SIFT. A partir da aplicação da metodologia para se otimizar cada um dos casos, foi comparada a eficiência tanto das ferramentas de análise de código, quanto das ferramentas de otimização, bem como a validade da metodologia proposta / This project presents a methodology applied to analyze the viability of C source code optimization for the Nios II embedded processor. This methodology utilizes the gprof and performance counter source code analysis tools to profile the source code of an application, and identify its critical time consuming parts. The optimization of C source code for the Nios II processor was performed using custom instructions and an automatic source code acceleration tool, the C2H compiler. Three algorithms were chosen as study cases, based on their importance to mobile robotics. Those were the gaxpy, EKF and SIFT algorithms. After applying the presented methodology to optimize each study case, efficiency comparisons were made between the source code analysis tools, as well between the optimization tools, in order to validate the presented methodology

A tendência de integração de diversos componentes em um único chip tem proporcionado um aumento da complexidade dos sistemas computacionais. Tanto as indústrias quanto o meio acadêmico estão em busca de técnicas que possibilitem diminuir o tempo e o esforço gastos com a verificação no processo de desenvolvimento de hardware, a fim de garantir qualidade, robustez e confiabilidade a esses dispositivos. De forma a contribuir para várias aplicações envolvendo a verificação de sistemas, tais como busca por erros de projeto, avaliação de desempenho, otimização de algoritmos e extração de dados do sistema, o presente trabalho propõe um sistema de monitoramento baseado em computação reconfigurável, capaz de observar de forma não intrusiva o comportamento de um SoC (System-on-Chip) em tempo de execução. Tal sistema é composto por um módulo de monitoramento responsável por captar informações de execução de software em um processador embarcado e uma ferramenta de análise, chamada ACAD, que interpreta esses dados. Por meio da realização de experimentos, verificou-se que o sistema desenvolvido foi capaz de fornecer dados fiéis sobre a quantidade de acessos a memória ou a outros periféricos, tempos de execução de porções (ou a totalidade) do código e número de vezes que cada instrução foi executada. Esses resultados permitem traçar, de maneira precisa, o comportamento de um software executado no processador softcore Nios II, contribuindo assim para facilitar o processo de verificação em sistemas baseados em computação reconfigurável / The trend of integrating several components on a single chip has motivated an increase in the complexity of computing systems. Both industry and academy are in search of new techniques that allow time and effort spent with verification on hardware development process to be reduced to guarantee quality, robustness, reability to these devices. In order to contribute to applications in the system verification area, such as search for design errors, performance evaluation, algorithm optimization and data extraction from the system, this work proposes a monitoring system based on reconfigurable computing. This system must be able to have a run-time non-intrusive probing of a System-on-Chip behaviour. It is formed by a monitoring core responsible for capturing software execution information of a embedded processor and an analysis tool, called ACAD, that decodes the data. Empirically, the implemented system was able to provide precise data about the amount of memory and other peripherals accesses, time measurement for sections (or the entire) of the source code, and number of times each instruction was executed. These results allow to draw, in accurate way, the behaviour of a software executed on the softcore Nios II processor, collaborating to make the verification process of systems based on reconfigurable computing easier