Made available in DSpace on 2015-05-14T12:36:54Z (GMT). No. of bitstreams: 1 arquivototal.pdf: 2004014 bytes, checksum: 3d8ca87826ca89996bb9c71a82501746 (MD5) Previous issue date: 2010-03-04 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / In this work, we present the development of an embedded system prototyping with soft-core Nios II and FPGA for a holter monitor that implements data compression, using the PPM Algorithm, and simulate ECG signals through the implementation of the Fourier series. Through a holter monitor, cardiologists can obtain ECG signals, serving as the basis for the perception of symptoms and activities of patients. These signals are captured and recorded by monitors in periods greater than or equal to 24 hours, requiring large storage size to store them, therefore increasing cost of the monitor. Using the PPM algorithm, a monitor holter can considerably reduce the size of the signals stored, thus reducing storage space and cost of device, addition to allow rapid transmission of the data. Integrating the ECG signal simulator to the device, is possible to generate samples of ECG via the embedded system, saving time and eliminating difficulties in obtaining signals, compared with the capture of real ECG signals by invasive and noninvasive methods. It enables the analysis and study of normal and abnormal ECGs. An embedded system on programmable chip (SOPC) was prototyped with a development kit containing peripherals and FPGA chip compatible with the Nios II. Architecture soft-core was set to compact operating system and software modules have been successfully developed, ported and validated on this platform. / Neste trabalho, é apresentado o desenvolvimento de um sistema embarcado com prototipagem em FPGA contendo instanciação do processador soft-core Nios II (SOPC System on a Programmable Chip), para um monitor holter que implementa compressão de dados, utilizando o algoritmo PPM, e simula sinais ECG através da implementação das Séries de Fourier. Através de um monitor holter, cardiologistas podem obter sinais ECG, que servem de base para a percepção de sintomas e atividades em pacientes, captados e armazenados pelos monitores em períodos maiores ou iguais a 24 horas, requisitando grandes espaços de armazenamento, aumentando, assim, o custo deste monitor. Utilizando o PPM, o dispositivo desenvolvido poderá reduzir consideravelmente a quantidade de dados armazenados, reduzindo, portanto, o espaço de armazenamento e o custo do dispositivo, permitindo ainda a rápida transmissão dos dados. Integrando o simulador de sinais ECG ao dispositivo, possibilita-se a geração de amostras de sinais eletrocardiográficos através do sistema embarcado, economizando tempo e eliminando dificuldades na obtenção de sinais, em comparação com a captação real de sinais ECG através de métodos invasivos e nãoinvasivos. O mesmo permite a análise e o estudo de sinais ECG normais e anormais. Um sistema embarcado em chip programável (SOPC) foi prototipado com uma placa contendo periféricos e uma pastilha FPGA dotada de compatibilidade com o Nios II; a arquitetura do soft-core foi configurada em sistema operacional compacto e módulos de software foram exitosamente desenvolvidos, portados e validados sobre essa plataforma.

Made available in DSpace on 2015-05-14T12:36:55Z (GMT). No. of bitstreams: 1 arquivototal.pdf: 2425731 bytes, checksum: 3f05e964526e281aa2761b2a01cac8f6 (MD5) Previous issue date: 2010-03-05 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / The present study portrays the development of a telemetric system integrating wireless sensor networks and data processing into an embedded system for monitoring vehicles in metropolitan railway networks, enabling real-time monitoring of train movements. The main objective of this system is to allow constant evaluation of numerous factors which can influence train performance, such as speed and pressure in air bags. By so doing, it may become possible to generate information so as to facilitate intervention strategies, thereby preventing the partial or total degradation of the transport services provided to the population. In order to perform real-time telemetry, wireless sensor networks with ZigBee technology will be mounted alongside the entire route of the train traffic. These networks capture and transmit data collected in each train until they reach base stations where a processing embedded system in an FPGA is responsible for receiving the data, performing the necessary calculations and sending the obtained information to a central monitoring system through an Ethernet network. The embedded system functions as a data server providing information to a monitoring system installed in the Operational Control Center (OCC) and in other sectors requiring this information. The use of a dedicated processing device such as an FPGA gives the system far greater efficiency than that typically found in general purpose processors. Furthermore, it allows the customization of the hardware, thus reducing the final cost of the system. The monitoring system installed in the OCC is responsible for managing the storage and display of the data received. It will display the data in tables and graphs in real time, enabling the traffic controllers to analyze the operation of each train and also to detect possible problems. The system also stores the data in a database for further study. Keywords: Telemetry, Wireless Sensor Networks, ZigBee Protocol, Embedded Systems, Nios II processor, FPGA. / Este trabalho apresenta o desenvolvimento de um sistema telemétrico que integra redes de sensores sem fio e processamento de dados em sistema embarcado para monitoramento de veículos em redes de transportes metroferroviários, possibilitando um acompanhamento em tempo real do movimento dos trens. Este sistema tem como principal objetivo permitir uma constante avaliação de vários fatores que influenciam o desempenho dos trens, como velocidade e pressão nas bolsas de ar, de forma a gerar informações que possibilitem estratégias de operação e manutenção, evitando assim uma degradação parcial ou total dos serviços de transporte prestados à população. Para realizar a telemetria em tempo real, redes de sensores sem fio com tecnologia ZigBee são montadas em toda a via de tráfego. Estas redes realizam a captação e envio dos dados coletados em cada trem até estações base onde um sistema de tratamento embarcado em um FPGA fica encarregado de receber os dados, realizar os cálculos necessários e enviar as informações obtidas, através de uma rede ethernet, a um sistema central de supervisão. O sistema embarcado atua como um servidor de dados disponibilizando informações para um sistema de supervisão instalado no Centro de Controle de Operações (CCO) e em outros setores que necessitem destas informações. A utilização de um dispositivo de processamento dedicado, como uma FPGA, proporciona ao sistema uma eficiência muito maior do que normalmente é encontrada em processadores de uso geral, além de permitir a customização do hardware, reduzindo o custo final do sistema. O sistema de supervisão instalado no CCO é responsável por gerenciar o armazenamento e a visualização dos dados recebidos. Ele exibe os dados em tabelas e gráficos em tempo real permitindo aos controladores de tráfego analisar o funcionamento de cada trem e detectar possíveis problemas. O sistema também armazena os dados em um banco de dados para realização de estudos posteriores.

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Network on Chip (NoC) has emerged as a competitive and efficient communication infrastructure for the core based design of System on Chip. Resource (core), router and interface between router and core are the three main parts of a NoC. Each core communicates with the network through the interface, also called Resource Network Interface (RNI). One approach to speed up the design at NoC based systems is to develop standardized RNI. Design of RNI depends to some extent on the type of routing technique used in NoC. Control of route decision base the categorization of source and distributed routing algorithms. In source routing a complete path to the destination is provided in the packet header at the source, whereas in distributed routing, the path is dynamically computed in routers as the packet moves through the network. Buffering, flitization, deflitization and transfer of data from core to router and vice versa, are common responsibilities of RNI in both types of routing. In source routing, RNI has an extra functionality of storing complete paths to all destinations in tables, extracting path to reach a desired destination and adding it in the header flit. In this thesis, we have made an effort towards designing and prototyping a standardized and efficient RNI for both source and distributed routing. VHDL is used as a design language and prototyping of both types RNI has been carried out on Altera DE2 FPGA board. Testing of RNI was conducted by using Nios II soft core. Simulation results show that the best case flit latency, for both types RNI is 4 clock cycles. RNI design is also resource efficient because it consumes only 2% of the available resources on the target platform.

<p>Network on Chip (NoC) has emerged as a competitive and efficient communication infrastructure for the core based design of System on Chip. Resource (core), router and interface between router and core are the three main parts of a NoC. Each core communicates with the network through the interface, also called Resource Network Interface (RNI). One approach to speed up the design at NoC based systems is to develop standardized RNI. Design of RNI depends to some extent on the type of routing technique used in NoC. Control of route decision base the categorization of source and distributed routing algorithms. In source routing a complete path to the destination is provided in the packet header at the source, whereas in distributed routing, the path is dynamically computed in routers as the packet moves through the network. Buffering, flitization, deflitization and transfer of data from core to router and vice versa, are common responsibilities of RNI in both types of routing. In source routing, RNI has an extra functionality of storing complete paths to all destinations in tables, extracting path to reach a desired destination and adding it in the header flit. In this thesis, we have made an effort towards designing and prototyping a standardized and efficient RNI for both source and distributed routing. VHDL is used as a design language and prototyping of both types RNI has been carried out on Altera DE2 FPGA board. Testing of RNI was conducted by using Nios II soft core. Simulation results show that the best case flit latency, for both types RNI is 4 clock cycles. RNI design is also resource efficient because it consumes only 2% of the available resources on the target platform.</p>