Este projeto apresenta uma metodologia aplicada à análise da viabilidade de se otimizar código fonte C para o processador embarcado Nios II. Esta metodologia utiliza ferramentas de análise de código que traçam o perfil da aplicação, identificando suas partes críticas em relação ao tempo de execução, as quais são o gprof e o performance counter. Para otimizar o código para o processador Nios II, são utilizadas tanto instruções customizadas quanto uma ferramenta automática de aceleração de código, o compilador C2H. Como casos de estudo, foram escolhidos três algoritmos devido à sua importância no campo da robótica móvel, sendo eles o gaxpy, o EKF e o SIFT. A partir da aplicação da metodologia para se otimizar cada um dos casos, foi comparada a eficiência tanto das ferramentas de análise de código, quanto das ferramentas de otimização, bem como a validade da metodologia proposta / This project presents a methodology applied to analyze the viability of C source code optimization for the Nios II embedded processor. This methodology utilizes the gprof and performance counter source code analysis tools to profile the source code of an application, and identify its critical time consuming parts. The optimization of C source code for the Nios II processor was performed using custom instructions and an automatic source code acceleration tool, the C2H compiler. Three algorithms were chosen as study cases, based on their importance to mobile robotics. Those were the gaxpy, EKF and SIFT algorithms. After applying the presented methodology to optimize each study case, efficiency comparisons were made between the source code analysis tools, as well between the optimization tools, in order to validate the presented methodology

Companies developing integrated circuits are expected to enhance their products’ performance at every new release, while reducing size and power consumption. The demand for more elaborate and diverse functionality, together with a reduced time-to-market, irremediably raises costs and increases the probability of bugs. Even high-performance ASICs are not immune: the complexity of the design flow implies significant non-recurring engineering and production costs. Similar challenges affect the FPGA design flow, where the allocation of programmable logic requires considerable engineering effort. Moreover, due to the limited visibility of internal operations, isolating and back-tracing malfunctions are open challenges. Ericsson AB is exploring novel approaches to deal with this complex ecosystem.This thesis investigates the feasibility and the benefits of a flexible design approach, by developing and characterizing a Proof-of-Concept (PoC) transceiver handler for highspeed link applications. The flexibility lies in the software-based controller, exploited to handle the reset and dynamic reconfiguration of a transceiver physical layer (PHY). The objective of the software implementation is to simplify error detection and on-the-fly modification compared to a traditional HW-based controller. The firmware, running on a Nios II soft-core processor, drives the control signals while monitoring the transceiver’s status. Unexpected synchronization losses are handled by a dedicated Interrupt Service Routine.The correct HW/SW interaction has been tested through simulation, whereas the software profiling proves that the timing requirements are met (only 167µs are spent on the reset sequence). Finally, the PoC has been benchmarked against an analogous system with a traditional HW-based controller, to evaluate the drawbacks of the introduction of a soft-core processor (in terms of logic utilization and power consumption).Despite the promising engineering effort reduction, further research is required to scale up the system and move from the PoC stage towards product release. / Företag som utvecklar integrerade kretsar förväntas öka prestandan i nya produkter, och samtidigt reducera storlek samt effektförbrukning. Efterfrågan på mer komplicerad funktionalitet, tillsammans med förkortad time-to-market, orsakar oundvikligen högre kostnader och ökad sannolikhet för buggar. Även högprestererande ASICs drabbas av detta: det komplicerade designflödet resulterar i signifikanta engångskostnader för teknisk utveckling samt tillverkning. Liknande utmaningar påverkar designflödet hos FPGA:er, där allokeringen av programmerbar logik kräver påtagligt utvecklingsarbete. Eftersom insynen i interna operationer är begränsad är isolation och spårning av fel aktuella utmaningar. Ericsson AB utforskar nya tillvägagångssätt för att hantera sådana komplexa ekosystem.Det här examensarbetet undersöker genomförbarheten och fördelarna med ett flexibelt tillvägagångssätt för design, genom utveckling och karaktärisering av ett konceptbevis för en transceiver-hanterare för höghastighetslänkar. Flexibiliteten realiseras med en mjukvarubaserad kontroller som används för att hantera återställningssignaler och dynamisk rekonfigurering av en transceiver (PHY). Målet med mjukvaruimplementationen är att förenkla feldetektion samt modifikation i realtid, jämfört med en traditionell hårdvarubaserad kontroller. Mjukvaran, som körs på en Nios II soft-coreprocessor, driver styrsignaler och övervakar transceiverns status. Oväntade synkroniseringsförluster hanteras av en dedikerad avbrottshanteringsrutin. Simulationer har gjorts för att testa korrekt interaktion mellan hårdvara och mjukbara. Profilering av mjukvara visar att timingkraven uppfylls (återställningssekvensen tar endast 167 µs). Avslutningsvis har konceptbeviset jämförts med ett likvärdigt hårdvarubaserat system för att utvärdera nackdelarna med introduktionen av Nios II (vad gäller resursanvändningen och effektförbrukningen).Trots lovande resultat är den begränsade detaljnivån i konceptbeviset en tydlig begränsning. Vidare arbete måste göras för att skala upp systemet och generalisera det här nya tillvägagångssättet.

Este trabalho de pesquisa tem por objetivo o desenvolvimento de um coprojeto de hardware/software para o algoritmo de correlação de imagens visando atingir um ganho de desempenho com relação à implementação totalmente em software. O trabalho apresenta um comparativo entre um conjunto bastante amplo e significativo de configurações diferentes do soft-processor Nios II implementadas em FPGA, inclusive com a adição de novas instruções dedicadas. O desenvolvimento do co-projeto foi feito com base em uma modificação do método baseado em profiling adicionando-se um ciclo de desenvolvimento e de otimização de software. A comparação foi feita com relação ao tempo de execução para medir o speedup alcançado durante o desenvolvimento do co-projeto que atingiu um ganho de desempenho significativo. Também analisou-se a influência de estruturas de hardware básicas e dedicadas no tempo de execução final do algoritmo. A análise dos resultados sugere que o método se mostrou eficiente considerando o speedup atingido, porém o tempo total de execução ainda ficou acima do esperado, considerando-se a necessidade de execução e processamento de imagens em tempo real dos sistemas de navegação robótica. No entanto, destaca-se que as limitações de processamento em tempo real estão também ligadas as restrições de desempenho impostas pelo hardware adotado no projeto, baseado em uma FPGA de baixo custo e capacidade média / This work presents a FPGA based hardware/software co-design for image normalized cross correlation algorithm. The main goal is to achieve a significant speedup related to the execution time of the all-software implementation. The co-design proposed method is a modified profiling-based method with a software development step. The executions were compared related to execution time resulting on a significant speedup. To achieve this speedup a comparison between 21 different configurations of Nios II soft-processor was done. Also hardware influence on execution time was evaluated to know how simple hardware structures and specific hardware structures influence algorithm final execution time. Result analysis suggest that the method is very efficient considering achieved speedup but the final execution time still remains higher, considering the need for real time image processing on robotic navigation systems. However, the limitations for real time processing are a consequence of the hardware adopted in this work, based on a low cost and capacity FPGA

Este trabalho de pesquisa tem por objetivo o desenvolvimento de um coprojeto de hardware/software para o algoritmo de correlação de imagens visando atingir um ganho de desempenho com relação à implementação totalmente em software. O trabalho apresenta um comparativo entre um conjunto bastante amplo e significativo de configurações diferentes do soft-processor Nios II implementadas em FPGA, inclusive com a adição de novas instruções dedicadas. O desenvolvimento do co-projeto foi feito com base em uma modificação do método baseado em profiling adicionando-se um ciclo de desenvolvimento e de otimização de software. A comparação foi feita com relação ao tempo de execução para medir o speedup alcançado durante o desenvolvimento do co-projeto que atingiu um ganho de desempenho significativo. Também analisou-se a influência de estruturas de hardware básicas e dedicadas no tempo de execução final do algoritmo. A análise dos resultados sugere que o método se mostrou eficiente considerando o speedup atingido, porém o tempo total de execução ainda ficou acima do esperado, considerando-se a necessidade de execução e processamento de imagens em tempo real dos sistemas de navegação robótica. No entanto, destaca-se que as limitações de processamento em tempo real estão também ligadas as restrições de desempenho impostas pelo hardware adotado no projeto, baseado em uma FPGA de baixo custo e capacidade média / This work presents a FPGA based hardware/software co-design for image normalized cross correlation algorithm. The main goal is to achieve a significant speedup related to the execution time of the all-software implementation. The co-design proposed method is a modified profiling-based method with a software development step. The executions were compared related to execution time resulting on a significant speedup. To achieve this speedup a comparison between 21 different configurations of Nios II soft-processor was done. Also hardware influence on execution time was evaluated to know how simple hardware structures and specific hardware structures influence algorithm final execution time. Result analysis suggest that the method is very efficient considering achieved speedup but the final execution time still remains higher, considering the need for real time image processing on robotic navigation systems. However, the limitations for real time processing are a consequence of the hardware adopted in this work, based on a low cost and capacity FPGA

<p>Integrated systems become larger and more complicated every day while time to market is shortened. Due to this, there is a need for flexible hardware platforms that use programmable logic not only for custom hardware but also for realizing embedded processors.</p><p>This thesis aims to select a suitable, FPGA targeted, soft processor core and adapt the real-time operating system OSE_ck to run on the selected target. A study of possibilities to integrate setup and configuration of OSE_ck into the processor’s IDE is also performed.</p><p>Studies of OSE_ck and the two processor candidates MicroBlaze and Nios II have been performed. The processor study showed that MicroBlaze and Nios II have a very similar architecture and both are suitable to host OSE_ck. MicroBlaze was chosen as target processor mainly because of more available documentation regarding operating system integration.</p><p>Performance and footprint was measured with OSE_ck on MicroBlaze. The performance figures indicate that MicroBlaze can not be expected to have the same processing power as hard processors but works well as a control processor. To achieve high application performance, custom hardware accelerators can be connected. Integration investigations and tests have been performed with the goal of making an interface that conforms to the normal MicroBlaze design flow.</p><p>OSE_ck has been successfully adapted to run on MicroBlaze and integration in the development environment is possible although some steps have to be done manually. Alternative integration options are discussed.</p>

The goal of this bachelor thesis work was to establish a cable connection between an analogue interface board, containing a 16 bit analogue to digital converter, and a DE2 board in order to allow for digital data transmission between the two boards. The DE2 board includes an FPGA which was configured to contain a Nios II softcore microprocessor for handling the tasks of reading and saving the 16 bit digital words transmitted over the cable as well as controlling the analogue to digital converter on the interface board. During the project work various tasks had to be fulfilled which included soldering the cable for parallel transmission of the 16 bit digital data words and the control signals between the boards as well as adjusting the analogue interface board with the correct voltage supplies and jumper settings. Furthermore the hardware circuit insidethe FPGA had to be configured and the program running on the Nios II processor had to be written in C language.

With advancement in automotive systems, it is not just the combination of mechanical devices like in old days. Almost all the systems of today's modern car are controlled electronically by a number of ECUs (Electronics Control Unit) with the combination of sensor modules. To exchange information between the ECU and sensor modules a number of communication standards are used. The most commonly used standards are CAN, LIN, and PWM etc. The data transmission between the ECU and sensor modules can be easily established with a PWM (Pulse Width Modulation) techniques in comparison with CAN or LIN. PWM provide a convenient solution in terms of cost and performance when the data-rate is up to 10-bits. While for higher resolution data rates its performance is not satisfied. Extra effort is needed to implement diagnostic information for the integrity of data. Also, the accuracy of PWM signal is dependent on the noise voltage and channel bandwidth. In 10-bit system a single bit is represented by 4mV which face serious problem in automotive system due to the noise voltage pulses which effect the resolution of the PWM. The alternative solution for safe and high data rate which is more than 10-bit resolution is to used CAN and LIN protocols. Both CAN and LIN have availability of diagnostic modes for an ensured data transmission. Also, their capabilities for interconnecting a number of nodes (sensors-modules) on the same network can significantly reduce the wiring cost. But in automotive a number of systems need to communicate through point-to-point link, and it seem to be too expensive to used CAN and LIN for point-to-point communication because of its development complexity and wiring cost for a standalone system. To overcome these issues and to provide an alternative low-cost solution the SAE (Society of Automotive Engineers) developed a 3-wire new digital point-to-point protocol called SENT. SENT (Single Edge Nibble Transmission) Protocol is now an international standard (SAE J2716). SENT is unidirectional point-to-point communication protocol, which can be used for high resolution data transmission between sensor module and ECU. The data are transmitted by sensor module in a series of pulses each pulse is 4-bit (one nibble) long and the data are measured between two falling edges by the receiving module. There are total of nine pulses which defined the SENT frame. The first pulse is called calibration pulse, it is used for compensating to recalibrate all the other pulses in case of transmitter clock deviation, this is the best feature of SENT and can be implemented in the decoder design. This thesis work focuses on the development of SENT protocol decoder and its signal robustness analysis in comparison with the conventional PWM signal. Our first goal is to developed SENT-Protocol decoder in software on the available microcontrollers is to check how much memory foot print is used and how much the processor overhead. Two platforms have been used for this purpose. First, two implementation designs prototype were made with fixed-point and floating-point development techniques on the 32-bit platform for SENT decoder. Secondly SENT-decoder were developed with 8-bit platform and compared with the two previous designs to check how much memory foot print is used and how much is the processor overhead. Finally, the signal integrity analysis has been performed for PWM and SENT signal using spice simulation. The purpose is to check the maximum data rate limit that the PWM signal support without creating any bit error in the transmitted signal. The same data rate is then used for SENT signal to be compared with PWM signal.

Integrated systems become larger and more complicated every day while time to market is shortened. Due to this, there is a need for flexible hardware platforms that use programmable logic not only for custom hardware but also for realizing embedded processors. This thesis aims to select a suitable, FPGA targeted, soft processor core and adapt the real-time operating system OSEck to run on the selected target. A study of possibilities to integrate setup and configuration of OSEck into the processor’s IDE is also performed. Studies of OSEck and the two processor candidates MicroBlaze and Nios II have been performed. The processor study showed that MicroBlaze and Nios II have a very similar architecture and both are suitable to host OSEck. MicroBlaze was chosen as target processor mainly because of more available documentation regarding operating system integration. Performance and footprint was measured with OSEck on MicroBlaze. The performance figures indicate that MicroBlaze can not be expected to have the same processing power as hard processors but works well as a control processor. To achieve high application performance, custom hardware accelerators can be connected. Integration investigations and tests have been performed with the goal of making an interface that conforms to the normal MicroBlaze design flow. OSEck has been successfully adapted to run on MicroBlaze and integration in the development environment is possible although some steps have to be done manually. Alternative integration options are discussed.

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Made available in DSpace on 2015-05-14T12:36:41Z (GMT). No. of bitstreams: 1 arquiuvototal.pdf: 6365528 bytes, checksum: 4e27c7390c2e3c53b8c85b58dabd1b55 (MD5) Previous issue date: 2012-08-20 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - CAPES / This work presents a monitoring infrastructure for people in a situation of home care through the integration of wireless sensor networks and data processing in embedded systems, enabling a real-time monitoring of the clinical picture of each patient. To perform real-time telemetry, a sensor network with ZigBee technology was set and some biological signals were captured in order to validate the proposed infrastructure. This network performs the capture and transmission of data collected to base stations where a treatment system embedded in an FPGA is instructed to receive data, perform the necessary calculations and send the information obtained through an Ethernet network to a central installed in a monitoring central station. The use of a dedicated processing device such as an FPGA, provides a much greater efficiency than is typically found in general purpose processors and allows the customization of the hardware. Besides, reduces the final cost of the system. It also presented the integration of Arthron and InteliCare. Arthron is tool that works with flow distribution. This integration allows more real experiences of telemedical procedures so that you can have in a single transmission, audio, video, and biological signals. The monitoring system installed in the central station is responsible for storage and display the received data. It will display data in tables and graphs in real time and allow a team of experts make decisions and guide patients and / or their caregivers to perform a certain procedure. / Este trabalho apresenta uma infraestrutura de monitoramento para pessoas em situação de internação domiciliar através da integração de redes de sensores sem fio e processamento de dados em sistemas embarcados, possibilitando um acompanhamento em tempo de execução (online) do quadro clínico de cada paciente. Para realizar a telemetria online, uma rede de sensores com tecnologia ZigBee, foi montada e alguns sinais biológicos foram captados de forma a validar a infraestrutura proposta. Esta rede realiza a captação e envio dos dados coletados até estações base onde um sistema de tratamento embarcado em um FPGA fica encarregado de receber os dados, realizar os cálculos necessários e enviar as informações obtidas, através de uma rede Ethernet, a um sistema central de supervisão instalado em uma central de monitoramento. A utilização de um dispositivo de processamento dedicado, como um FPGA, proporciona ao sistema uma eficiência muito maior do que normalmente é encontrada em processadores de uso geral além de permitir a customização do hardware reduzindo o custo final do sistema. É apresentada também a integração da infraestrutura InteliCare com a ferramenta de distribuição de fluxos Arthron. Esta integração permite tornar mais real a experiência de colaboração em procedimentos médicos de forma que é possível ter numa mesma transmissão, áudio, vídeo e sinais biológicos. O sistema de supervisão instalado na central de monitoramento é responsável por gerenciar o armazenamento e a visualização dos dados recebidos. Ele exibe os dados em tabelas e gráficos em tempo de execução e permitirá que uma equipe de especialistas tome decisões e oriente os pacientes e/ou seus cuidadores para realizar determinado procedimento.