Las actuales arquitecturas de m�ltiples n�cleos como los chip multiprocesadores (CMP) y soluciones multiprocesador para sistemas dentro del chip (MPSoCs) han adoptado a las redes dentro del chip (NoC) como elemento -ptimo para la inter-conexi-n de los diversos elementos de dichos sistemas. En este sentido, fabricantes de CMPs y MPSoCs han adoptado NoCs sencillas, generalmente con una topolog'a en malla o anillo, ya que son suficientes para satisfacer las necesidades de los sistemas actuales. Sin embargo a medida que los requerimientos del sistema -- baja latencia y alto rendimiento -- se hacen m�s exigentes, estas redes tan simples dejan de ser una soluci-n real. As', la comunidad investigadora ha propuesto y analizado NoCs m�s complejas. No obstante, estas soluciones son m�s dif'ciles de implementar -- especialmente los enlaces largos -- haciendo que este tipo de topolog'as complejas sean demasiado costosas o incluso inviables. En esta tesis, presentamos una metodolog'a de dise-o que minimiza la p�rdida de prestaciones de la red debido a su implementaci-n real. Los principales problemas que se encuentran al implementar una NoC son los conmutadores y los enlaces largos. En esta tesis, el conmutador se ha hecho modular, es decir, formado como uni-n de m-dulos m�s peque-os. En nuestro caso, los m-dulos son id�nticos, donde cada m-dulo es capaz de arbitrar, conmutar, y almacenar los mensajes que le llegan. Posteriormente, flexibilizamos la colocaci-n de estos m-dulos en el chip, permitiendo que m-dulos de un mismo conmutador est�n distribuidos por el chip. Esta metodolog'a de dise-o la hemos aplicado a diferentes escenarios. Primeramente, hemos introducido nuestro conmutador modular en NoCs con topolog'as conocidas como la malla 2D. Los resultados muestran como la modularidad y la distribuci-n del conmutador reducen la latencia y el consumo de potencia de la red. En segundo lugar, hemos utilizado nuestra metodolog'a de dise-o para implementar un crossbar distribuid / Roca Pérez, A. (2012). Floorplan-Aware High Performance NoC Design [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/17844

The notion of platform based design is considered as a viable solution to boost the design productivity by favouring reuse design methodology. With the scaling down of device feature size and scaling up of design complexity, throughput limitations, signal integrity and signal latency are becoming a bottleneck in future communication centric System-on-Chip (SoC) design. This has given birth to communication centric platform based designs. Development of heterogeneous multi-core architectures has caused the on-chip communication medium tailored for a specific application domain to deal with multidomain traffic patterns. This makes the current application specific communication centric platforms unsuitable for future SoC architectures. The work presented in this thesis, endeavours to explore the current communication media to establish the expectations from future on-chip interconnects. A novel communication centric platform based design flow is proposed, which consists of four communication centric platforms that are based on shared global bus, hierarchical bus, crossbars and a novel hybrid communication medium. Developed with a smart platform controller, the platforms support Open Core Protocol (OCP) socket standard, allowing cores to integrate in a plug and play fashion without the need to reprogram the pre-verified platforms. This drastically reduces the design time of SoC architectures. Each communication centric platform has different throughput, area and power characteristics, thus, depending on the design constraints, processing cores can be integrated to the most appropriate communication platform to realise the desired SoC architecture. A novel hybrid communication medium is also developed in this thesis, which combines the advantages of two different types of communication media in a single SoC architecture. The hybrid communication medium consists of crossbar matrix and shared bus medium . Simulation results and implementation of WiMAX receiver as a real-life example shows a 65% increase in data throughput than shared bus based communication medium, 13% decrease in area and 11% decrease in power than crossbar based communication medium. In order to automate the generation of SoC architectures with optimised communication architectures, a tool called SOCCAD (SoC Communication architecture development) is developed. Components needed for the realisation of the given application can be selected from the tool’s in-built library. Offering an optimised communication centric placement, the tool generates the complete SystemC code for the system with different interconnect architectures, along with its power and area characteristics. The generated SystemC code can be used for quick simulation and coupled with efficient test benches can be used for quick verification. Network-on-Chip (NoC) is considered as a solution to the communication bottleneck in future SoC architectures with data throughput requirements of over 10GB/s. It aims to provide low power, efficient link utilisation, reduced data contention and reduced area on silicon. Current on-chip networks, developed with fixed architectural parameters, do not utilise the available resources efficiently. To increase this efficiency, a novel dynamically reconfigurable NoC (drNoC) is developed in this thesis. The proposed drNoC reconfigures itself in terms of switching, routing and packet size with the changing communication requirements of the system at run time, thus utilising the maximum available channel bandwidth. In order to increase the applicability of drNoC, the network interface is designed to support OCP socket standard. This makes drNoC a highly reuseable communication framework, qualifying it as a communication centric platform for high data intensive SoC architectures. Simulation results show a 32% increase in data throughput and 22-35% decrease in network delay when compared with a traditional NoC with fixed parameters.

The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope. / The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope.

Les circuits intégrés devenant de plus en plus complexes, leur test demande des efforts considérables se répercutant sur le coût de développement et de production de ces composants. De nombreux travaux ont donc porté sur la réduction du coût de ce test en utilisant en particulier les techniques de compression de données de test. Toutefois ces techniques n'adressent que des coeurs numériques dont les concepteurs détiennent la connaissance de toutes les informations structurelles et donc en pratique n'adressent que le test de sous-blocs d'un système complet. Dans cette thèse, nous proposons tout d'abord une nouvelle technique de compression des données de test pour les circuits intégrés compatible avec le paradigme de la conception de systèmes (SoC) à partir de fonctions pré-synthétisées (IPs ou coeurs). Puis, deux méthodes de test des systèmes utilisant la compression sont proposées. La première est relative au test des systèmes SoC utilisant l'architecture de test IEEE 1500 (avec un mécanisme d'accès au test de type bus), la deuxième concerne le test des systèmes pour lesquels la communication interne s'appuie sur des structures de type réseau sur puce (NoC). Ces deux méthodes utilisent conjointement un ordonnancement du test des coeurs du système avec une technique de compression horizontale afin d'augmenter le parallélisme du test des coeurs constituant le système et ce, à coût matériel constant. Les résultats expérimentaux sur des systèmes sur puces de référence montrent des gains de l'ordre de 50% sur le temps de test du système complet. / While microelectronics systems become more and more complex, test costs have increased in the same way. Last years have seen many works focused on test cost reduction by using test data compression. However these techniques only focus on individual digital circuits whose structural implementation (netlist) is fully known by the designer. Therefore, they are not suitable for the testing of cores of a complete system. The goal of this PhD work was to provide a new solution for test data compression of integrated circuits taking into account the paradigm of systems-on-chip (SoC) built from pre-synthesized functions (IPs or cores). Then two systems testing method using compression are proposed for two different system architectures. The first one concerns SoC with IEEE 1500 test architecture (with bus-based test access mechanism), the second one concerns NoC-based systems. Both techniques use test scheduling methods combined with test data compression for better exploration of the design space. The idea is to increase test parallelism with no hardware extra cost. Experimental results performed on system-on-chip benchmarks show that the use of test data compression leads to test time reduction of about 50% at system level.

Submitted by Caroline Xavier (caroline.xavier@pucrs.br) on 2017-06-30T13:50:31Z No. of bitstreams: 1 DIS_RAMON_COSTI_FERNANDES_COMPLETO.pdf: 4552821 bytes, checksum: 31f78eb686d2c3126cf0abf4584de386 (MD5) / Made available in DSpace on 2017-06-30T13:50:31Z (GMT). No. of bitstreams: 1 DIS_RAMON_COSTI_FERNANDES_COMPLETO.pdf: 4552821 bytes, checksum: 31f78eb686d2c3126cf0abf4584de386 (MD5) Previous issue date: 2017-03-13 / A pr?xima gera??o de sistemas multiprocessados intra-chip, do ingl?s MultiProcessor Systems-on-Chip (MPSoC), comportar? centenas de elementos de processamento num ?nico chip, com a promessa de alta vaz?o de comunica??o, baixa lat?ncia e, preferencialmente, baixo consumo de energia. Devido ? elevada demanda de comunica??o paralela de aplica??es para MPSoCs, a rede intra-chip, do ingl?s Network-on-Chip (NoC), tem sido amplamente adotada como um meio de comunica??o confi?vel e escal?vel para MPSoCs. O espa?o de projeto para NoCs deve ser explorado para atender ? demanda das aplica??es atuais. Dentre os par?metros que definem uma NoC, o algoritmo de roteamento tem sido utilizado para prover servi?os como toler?ncia ? falhas, liberdade de deadlocks e de livelocks, assim como Quality of Service (QoS). Conforme a ado??o e complexidade de Systems-on-Chip (SoC) aumenta para sistemas embarcados, a preocupa??o com a prote??o de dados tamb?m torna-se um requisito para o projeto de MPSoCs. Atualmente, MPSoCs podem ser atacados explorando vulnerabilidades em hardware ou software, sendo o ?ltimo respons?vel por 80% dos incidentes de seguran?a em sistemas embarcados. A prote??o contra vulnerabilidades de software pode acontecer em: (i) N?vel de Aplica??o, utilizando t?cnicas como a criptografia, para evitar a transmiss?o de dados desprotegidos entre os elementos de um MPSoC, conhecidos como m?dulos de propriedade intelectual, do ingl?s Intellectual Property (IP); ou (ii) N?vel de Comunica??o, inspecionando ou filtrando elementos na arquitetura de interconex?o atrav?s de monitores de comunica??o ou firewalls, respectivamente. Portanto, um algoritmo de roteamento, ciente dos requisitos de seguran?a do sistema, deve oferecer prote??o ao utilizar rotas confi?veis na NoC, evitando elementos potencialmente maliciosos em rotas porventura inseguras. A principal contribui??o deste trabalho ? uma t?cnica de prote??o para NoCs que atua em n?vel de comunica??o, adaptando os algoritmos Segment-based Routing (SBR) e Region-based Routing (RBR) para que estes considerem aspectos de seguran?a do sistema, estes caracterizados por zonas de seguran?a definidas na NoC de acordo com o mapeamento de aplica??es nos IPs. A avalia??o da t?cnica de roteamento considera aspectos como a escalabilidade das tabelas de roteamento, a quantidade de rotas seguras definidas entre os IPs, e o impacto desta t?cnica de roteamento em aplica??es do benchmark NASA Numerical Aerodynamic Simulation (NAS) Parallel Bencharm (NPB). / The next generation of MultiProcessor Systems-on-Chip (MPSoC) will encompass hundreds of integrated processing elements into a single chip, with the promise of highthroughput, low latency and, preferably, low energy utilization. Due to the high communication parallelism required by several applications targeting MPSoC architectures, the Network-on-Chip (NoC) has been widely adopted as a reliable and scalable interconnection mechanism. The NoC design space should be explored to meet the demanding requirements of current applications. Among the parameters that define a NoC configuration, the routing algorithm has been employed to provide services such as fault tolerance, deadlock and livelock freedom, as well as Quality of Service (QoS). As the adoption and complexity of System-on-Chip (SoC) increases for embedded systems, the concern for data protection appears as a new design requirement. Currently, MPSoCs can be attacked by exploiting either hardware or software vulnerabilities, with the later responsible for 80% of the security incidents in embedded systems. Protection against software vulnerabilities can occur at (i) Application Level, by using techniques such as data encryption to avoid plain data transmissions between Intellectual Property (IP) modules; or (ii) Communication Level, inspecting or filtering elements at the interconnect fabric with communication monitors or firewalls, respectively. As such, a routing algorithm aware of security requirements could also offer protection utilizing trusted communication paths in the NoC, avoiding potential malicious elements in otherwise unsafe communication paths. The main contribution of this work is a NoC protection technique at communication level by adapting Segment-based Routing (SBR) and Region-based Routing (RBR) algorithms to consider system security requirements, characterized by security zones which are defined on the NoC according to the mapping of applications on IP modules. Evaluation of the proposed routing technique considers aspects such as the scalability of routing tables, the number of secure communication paths, and the impact of this technique on applications of the NASA Numerical Aerodynamic Simulation (NAS) Parallel Benchmark (NPB).

This thesis focuses on the issue of nursing care for adolescent boys who have undergone phimosis surgery. The nursing care is then evaluated according to the NANDA, NIC and NOC classification systems. The theoretical part deals with topics such as adolescence, phimosisa disease of the external genitalia of a man, preoperative and postoperative care for boys with phimosis, and the classification taxonomy of the NANDA, NIC and NOC classification systems, which represent the comprehensive standardized, but still evolving, nursing language. Available Czech and foreign literary sources were used for the compilation of the theoretical part of the stated subject. The empirical part of the thesis was processed using qualitative and quantitative research methods: content analyzes, modelling, thought experiment, structured and semi-structured interviews, and qualitative data analysis. Four objectives were defined. The way adolescent boys perceive and experience the bio-psycho-social aspects of the problems that the pre-op and post-op period brings, has been assessed using the NANDA, NIC and NOC classification systems. There were 46.66% of respondents with higher education, 53.34% of respondents with secondary education, and eight adolescent boys who had received phimosis surgery, all of whom contributed to the assessment. It was found that adolescent boys initially addressed their physician regarding the phimosis problem, because they had a sense of trust and anonymity, but also to some degree because of necessity. It is surprising that young men with this type of personal problem rather speak to their mothers. When it comes to peer relationships, the boys confide the problem to their peers, but they do not ask them for help in this area. The boys named the internet as the main source of information. The following assessments were made using the Fehring methods for determining the weighted scores. Out of 13 nursing diagnoses within the NNN classification systems there were 112 major and minor characteristics (41.18%) selected by the university educated respondents, 80 major and minor characteristics (29,41%) selected by by the secondary school educated respondents, and nine major and minor characteristics (3.31%) were selected by the adolescent boys. Out of the 15 nursing interventions published in the Nursing Interventions Classification (NIC), 203 major and minor characteristics (55.31%) were chosen by the university educated respondents and 235 major and minor characteristics (64.03%) were chosen by the secondary school educated respondents. Out of the 11 expected nursing outcomes published in the Nursing Outcomes Classification (NOC), 39 major and minor characteristics (15.42%) were selected by the university educated respondents, while 34 major and minor characteristics (13.44%) were selected by the secondary school educated respondents. By implementing the NANDA, NIC and NOC classification systems in nursing care one can expect to find solutions that help the professionals in nursing care to apply the nursing process effectively, and that allow nursing care to focus more on the individual needs of patients and to be improved in all areas.

This diploma thesis deals with the role of the child nurse in the adaptation of the newborn after delivery.In the theoretical part we devote to the available scientific knowledge focused on the course of pregnancy, the way of giving birth (vaginal and operative), assessment of postnatal adaptation of the newborn, breastfeeding and its importance. The essential part is mapping the role of child nurse in newborn care using the NOC system to evaluate their postnatal adaptation. The Czech and foreign literary sources were used for the theoretical part of the diploma thesis. The first aim of the diploma thesis was a detailed mapping of the role of the child nurse in postnatal adaptation of the newborn after physiological and operative delivery. Two research questions have been selected for its solution. The first research question was, what Apgar values the newborns show after the physiological and operative delivery. The second research question was the success of the first application of the newborn to breastfeeding within 30 minutes after physiological and operative delivery. The second aim of this diploma thesis was to verify the classification of the NOC on the evaluation of the newborn adaptation. For the solution, a research question has been determined, what is the opinion of nurses on the use of the NOC classification system in postnatal adaptation. For the empirical part of the research we have chosen a qualitatively quantitative strategy. Observation, individual semi-structured interviews with nurses and written filling of NOC classification system forms were used for data collection. The first research group was 10 newborns after the physiological - vaginal delivery and 10 newborns after the operative delivery by Caesarean section. The second research group consisted of 2 child nurses working with neonates as part of postnatal adaptation in Hospital Jihlava. Analyzing and interpreting the obtained results, we found out that newborns born by vaginal delivery had an average Apgar score of 8.03 and newborns born by Caesarean section had an average Apgar score of 9.50. The average values of the indicators in the NOC classification system code 0118 The adaptation of the newborn showed slightly poorer results after vaginal deliveries. Two groups of newborns that we followed did not match the generally expected results. Newborns after the Caesarean section are threatened by risk factors, but due to careful nursing care and gentle childbirth, such a risk does not occur and the process of postnatal adaptation can be successful. In the NOC classification system code 1000 Beginning of breastfeeding child showed the indicators at vaginal deliveries, at least 8 feedings per day and infant satisfaction after feeding, better results. In the NOC classification system code 1001 Beginning of breastfeeding mother the average values of breast suction indicators and satisfaction with the breastfeeding process resulted better in favour of neonates born vaginally compared to neonates after Caesarean section. As regards the success of the first feeding of neonates to breastfeeding within 30 minutes after delivery, a clearly superior result was obtained for newborns born vaginally. The conclusions drawn from our research in relation to child breastfeeding by mother confirm the clear benefit of vaginal births for the successful adaptation of newborns. A child nurse undoubtedly plays an important role in the assessment of postnatal adaptation of the newborn. The research of the diploma thesis shows that the classification system NOC is very well sophisticated in the context of a newborn adaptation and it is even detailed in connection with the follow-up and subsequent provision of newborn care. Its full use in current practice in the established care system of particular healthcare facilities is not possible due to insufficient staffing of the department. The existing documentation system does not provide reserves

Les variabilités du processus de fabrication des technologies avancées (typ. < 32nm) sont de plus en plus difficile à maîtriser. Elles impactent plus sévèrement la fréquence de fonctionnement et la consommation d'énergie, et induisent de plus en plus de défaillances dans le circuit. Ceci est particulièrement vrai pour les MPSoCs, où le nombre de coeurs de calculs est très important. Les besoins (performances, fonctionnalités, faible consommation, tolérance aux fautes) ne cessent de croître et les caractéristiques hétérogènes (fréquence, énergie, défaillances) rendent difficile la mise en oeuvre de systèmes répondant à ces exigences. Ces travaux s'inscrivent dans l'optique de traiter ces problèmes pour des systèmes MPSoCs massivement parallèles, basés sur une topologie en maille 2D. Cette thèse propose une méthodologie automatisée qui permet le placement et l'ordonnancement d'applications dans les systèmes ciblés. Les aspects variabilité, consommation et performance sont pris en compte. D'autre part, cette thèse propose une technique de placement adaptatif tolérant aux fautes basée sur une stratégie de recouvrement des erreurs. Cette stratégie permet de garantir la terminaison de l'application en présence de défaillances, sans avoir recours à la prise de « check-points ». Cette technique est complété par des algorithmes adaptatifs distribués, prenant en compte la variabilité et la consommation d'énergie. / With the advanced technologies (typ. < 32nm), it is more and more difficult to control the manufacturing variabilities. It impacts more severely the working frequency and the consumed energy, and induces more and more failure inside the device. This is particularly true for MPSoC with a large number of computing cores. With the increasing needs (performance, functionalities, low power, fault tolerance) and heterogeneous characteristics (frequency, energy, failures) it becomes difficult to apply to systems able to meet these requirements. This work focus on this perspective to deal with these issues for the massively parallel MPSoC, based on 2D mesh topology. This thesis proposes an automated methodology, allowing the mapping and scheduling of application on the targeted system. It takes into account the variability, energy and computing power. Furthermore, this thesis proposes a fault tolerant adaptive mapping technique, paired with an original failure recovering strategy. This strategy allows to guarantee the termination of the application in the presence of failures, without the check-point requirement. The technique has been extended with an adaptive distributed algorithm, taking into account the manufacturing variability and aimed at reducing the consumed energy.

Les progrès dans les technologies à base de semi-conducteurs et la demande croissante de puissance de calcul poussent vers une intégration dans une même puce de plus en plus de processeurs intégrés. Par conséquent les réseaux sur puce remplacent progressivement les bus de communication, ceux-ci offrant plus de débit et permettant une mise à l'échelle simplifiée. Parallèlement, la réduction de la finesse de gravure entraine une augmentation de la sensibilité des circuits au processus de fabrication et à son environnement d'utilisation. Les défauts de fabrication et le taux de défaillances pendant la durée de vie du circuit augmentent lorsque l'on passe d'une technologie à une autre. Intégrer des techniques de tolérance aux fautes dans un circuit devient indispensable, en particulier pour les circuits évoluant dans un environnement très sensible (aérospatial, automobile, santé, ...). Nous présentons dans ce travail de thèse, des techniques permettant d'améliorer la tolérance aux fautes des micro-réseaux intégrés dans des circuits évoluant dans un environnement difficile. Le NoC doit ainsi être capable de s'affranchir de la présence de nombreuses fautes. Les travaux publiés jusqu'ici proposaient des solutions pour un seul type de faute. En considérant les contraintes de surface et de consommation du domaine de l'embarqué, nous avons proposé un algorithme de routage adaptatif tolérant à la fois les fautes intermittentes, transitoires et permanentes. En combinant et adaptant des techniques existantes de retransmission de flits, de fragmentation et de regroupement de paquet, notre approche permet de s'affranchir de nombreuses fautes statiques et dynamiques. Les très nombreuses simulations réalisées ont permis de montrer entre autre que, l'algorithme proposé permet d'atteindre un taux de livraison de paquets de 97,68% pour un NoC 16x16 en maille 2D en présence de 384 liens défectueux simultanés, et 93,40% lorsque 103 routeurs sont défaillants. Nous avons étendu l'algorithme aux topologies de type tore avec des résultats bien meilleurs.Une autre originalité de cette thèse est que nous avons inclus dans cet algorithme une fonction de gestion de la congestion. Pour cela nous avons défini une nouvelle métrique de mesure de la congestion (Flit Remain) plus pertinente que les métriques utilisées et publiées jusqu'ici. Les expériences ont montré que l'utilisation de cette métrique permet de réduire la latence (au niveau du pic de saturation) de 2,5 % à 16,1 %, selon le type de trafic généré, par rapport à la plus efficace des métriques existante. La combinaison du routage adaptatif tolérant les fautes statiques et dynamiques et la gestion de la congestion offrent une solution qui permet d'avoir un NoC et par extension un circuit beaucoup plus résilient. / The quest for higher-performance and low-power consumption has driven the microelectronics' industry race towards aggressive technology scaling and multicore chip designs. In this many-core era, the Network-on-chip (NoCs) becomes the most promising solution for on-chip communication because of its performance scaling with the number of IPs integrated in the chip.Fault tolerance becomes mandatory as the CMOS technology continues shrinking down. The yield and the reliability are more and more affected by factors such as manufacturing defects, process variations, environment variations, cosmic radiations, and so on. As a result, the designs should be able to provide full functionality (e.g. critical systems), or at least allow degraded mode in a context of high failure rates. To accomplish this, the systems should be able to adapt to manufacturing and runtime failures.In this thesis, some techniques are proposed to improve the fault tolerance ability of NoC based circuits working in harsh environments. As previous works allow the handling of one type of fault at a time, we propose here a solution where different kinds of faults can be tolerated concurrently.Considering constraints such as area and power consumption, a fault tolerant adaptive routing algorithm was proposed, which can cope with transient, intermittent and permanent faults. Combined with some existing techniques, like flit retransmission and packet fragmentation, this approach allows tolerating numerous static and dynamic faults. Simulations results show that the proposed solution allows a high packet delivery success rate: for a 16x16 2D Mesh NoC, 97.68% in the presence of 384 simultaneous link faults, and 93.40% with the presence of 103 simultaneous router faults. This success rate is even higher when this algorithm is extended to NoCs with Tore topology. Another contribution of this thesis is the inclusion of a congestion management function in the proposed routing algorithm. For this purpose, we introduce a novel metric of congestion measurement named Flit Remain. The experimental results show that using this new congestion metric allows a reduction of the average latency of the Network on Chip from 2.5% to 16.1% when compared to the existing metrics.The combination of static and dynamic fault tolerant and adaptive routing and the congestion management offers a solution, which allows designing a NoC highly resilient.

The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope. / The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope.