The ferroelectricity in fluorite structure based hafnium oxide (HfO2) material expanded the horizon for realizing nonvolatile ferroelectric memory concepts. Due to the excellent HfO2 ferroelectric film properties, CMOS compatibility, and scalability; the material is foreseen as a replacement of the lead based ferroelectric materials with a big game changing potential for the emerging ferroelectric memories. In this thesis, the development of novel memory concepts based on the ferroelectric or antiferroelectric HfO2 material is reported. The ferroelectric field effect transistor (FeFET) memory concept offers a low power, high-speed, nonvolatile, and one cell memory solution ideal for embedded memory realization. As an emerging concept based on a novel ferroelectric material, the FeFET is challenged with key performance aspects intrinsic to the underlying physics of the device. A central part of this thesis is the development of FeFET through material and gate stack engineering, in turn leading to innovative novel device concepts. The conceptual innovation, process development, and electrical assessment are explored for an ferroelectric or antiferroelectric HfO2 based nonvolatile memories with focus on the underlying device physics. The impact of the ferroelectric material on the FeFET physics is explored via the screening of different HfO2 based ferroelectric materials, thicknesses, and the film doping concentration. The impact of material interfaces and substrate doping conditions are explored on the stack engineering level to achieve a low power and reliable FeFET. The material optimization leads to the concept of ferroelectric lamination, i.e. a dielectric interlayer between multi ferroelectric ones, to achieve a novel multilevel data storage in FeFET at reduced device variability. Toward a low power FeFET, the stack structure tuning and dual ferroelectric layer integration are explored through an MFM and MFIS integration in a single novel FeFET stack. The charge trapping effect during the FeFET switching captures the dynamics of the hysteresis polarization switching inside the stack with direct impact on the interfacial layer field. Even though manifesting as a clear drawback in FeFET operation, it can be utilized in Flash, leading to a novel hybrid low power and high-speed antiferroelectric based charge trap concept. Furthermore, the FeFET reliability is studied covering the role of operating temperature and the ferroelectric wakeup phenomenon observed in the FeFET. The temperature modulated operation, role of the high-temperature pyroelectric effect, and the temperature induced endurance and retention reliability are studied.:Table of Contents Abstract Table of Contents 1. Introduction 2. Fundamentals 2.1. Basics of Ferroelectricity 2.2. The FeFET Operation Principle and Gate Stack Theory 2.3. Structure and Outline of the PhD Thesis 3. The Emerging Memory Optimization Cycle: From Conceptual Design to Fabrication 3.1. The FeFET Conceptual Design and Layout Implementation 3.2. Gate First FeFET Fabrication: Material and Gate Stack Optimization 3.3. Novel Gate First based Memory Concepts: Device Integration and Stack Optimization 3.4. Device Characterization: Electrical Testing Schemes 4. The Emerging FeFET Memory: Material and Gate Stack Optimization 4.1. Material Aspect of FeFET Optimization: Role of the FE Material Properties 4.2. The Stack Aspect of FeFET Optimization: Role of the Interface Layer Properties 4.3. The Stack Aspect of FeFET Optimization: Role of the Substrate Implant Doping 4.4. Summary 5. A Novel Multilevel Cell FeFET Memory: Laminated HSO and HZO Ferroelectrics 5.1. The Laminate MFM and Stack Characteristics 5.2. The Laminate based FeFET Memory Switching 5.3. The Laminate FeFET Multilevel Coding Operation (1 bit, 2 bit, 3 bit/cell) 5.4. The Maximum Laminate FeFET MW Dependence on FE Stack Thickness 5.5. The Role of Wakeup and Charge Trapping 5.6. The Laminate MLC FeFET Area Dependence 5.7. The Laminate MLC Retention and Endurance 5.8. Impact of Pass Voltage Disturb on Laminate based NAND Array Operation 5.9. The Laminate FeFET based Synaptic Device 5.10. Summary 6. A Novel Ferroelectric MFMFIS FeFET: Toward Low Power and High-Speed NVM 6.1. The MFMFIS FeFET P-E and FET Characteristics 6.2. The MFMFIS based Memory Characteristics 6.3. The Impact of MFMFIS Stack Structure Tuning 6.4. The Maximum MFMFIS FeFET Memory Window 6.5. The Role of Device Scalability and Variability 6.6. The MFMFIS Area Tuning for Low Power Operation 6.7. The MFMFIS based FeFET Reliability 6.8. The Synaptic MFMFIS based FeFET 6.9. Summary 7. A Novel Hybrid Low Power and High-Speed Antiferroelectric Boosted Charge Trap Memory 7.1. The Hybrid Charge Trap Memory Switching Characteristics 7.2. The Role of Polarization Switching on Optimal Write Conditions 7.3. The Impact of FE/AFE Properties on the Charge Trap Maximum Memory Window 7.4. The Hybrid AFE Charge Trap Multi-level Coding and Array Operation 7.5. The Global Variability and Area Dependence of the Charge Trap Memory Window 7.6. The AFE Charge Trap Reliability 7.7. The Hybrid AFE Charge Trap based Synapse 7.8. Summary 8. The Emerging FeFET Reliability: Role of Operating Temperature and Wakeup Effect 8.1. The FeFET Temperature Reliability: A Temperature Modulated Operation 8.2. The FeFET Temperature Reliability: Role of the Pyroelectric Effect 8.3. The FeFET Temperature Reliability: Endurance and Retention 8.4. The Impact of Ferroelectric Wakeup on the FeFET Memory Reliability 8.5. Summary 9. Closure: What this Thesis has Solved? 9.1. How material selection/development influence the FeFET? 9.2. Why the FeFET Still Operates at High Write Conditions? 9.3. Why the FeFET Endurance is still a Challenge? 9.4. Can the FeFET become Multi-bit Storage Memory? 9.5. How the Scalability Determine FeFET Chances? 10. Summary 11. Bibliography List of symbols and abbreviations List of Publications Acknowledgment Erklärung

With the rise of computationally expensive application domains such as machine learning, genomics, and fluids simulation, the quest for performance and energy-efficient computing has gained unprecedented momentum. The significant increase in computing and memory devices in modern systems has resulted in an unsustainable surge in energy consumption, a substantial portion of which is attributed to the memory system. The scaling of conventional memory technologies and their suitability for the next-generation system is also questionable. This has led to the emergence and rise of nonvolatile memory ( NVM ) technologies. Today, in different development stages, several NVM technologies are competing for their rapid access to the market. Racetrack memory ( RTM ) is one such nonvolatile memory technology that promises SRAM -comparable latency, reduced energy consumption, and unprecedented density compared to other technologies. However, racetrack memory ( RTM ) is sequential in nature, i.e., data in an RTM cell needs to be shifted to an access port before it can be accessed. These shift operations incur performance and energy penalties. An ideal RTM , requiring at most one shift per access, can easily outperform SRAM . However, in the worst-cast shifting scenario, RTM can be an order of magnitude slower than SRAM . This thesis presents an overview of the RTM device physics, its evolution, strengths and challenges, and its application in the memory subsystem. We develop tools that allow the programmability and modeling of RTM -based systems. For shifts minimization, we propose a set of techniques including optimal, near-optimal, and evolutionary algorithms for efficient scalar and instruction placement in RTMs . For array accesses, we explore schedule and layout transformations that eliminate the longer overhead shifts in RTMs . We present an automatic compilation framework that analyzes static control flow programs and transforms the loop traversal order and memory layout to maximize accesses to consecutive RTM locations and minimize shifts. We develop a simulation framework called RTSim that models various RTM parameters and enables accurate architectural level simulation. Finally, to demonstrate the RTM potential in non-Von-Neumann in-memory computing paradigms, we exploit its device attributes to implement logic and arithmetic operations. As a concrete use-case, we implement an entire hyperdimensional computing framework in RTM to accelerate the language recognition problem. Our evaluation shows considerable performance and energy improvements compared to conventional Von-Neumann models and state-of-the-art accelerators.

Metal-Oxide-Silicon Field-Effect-Transistors with a layer of electrically isolated Si nanocrystals (NCs) embedded in the gate oxide are known to improve conventional floating gate flash memories. Data retention, program and erase speeds as well as the memory operation voltages can be substantially improved due to the discrete charge storage in the isolated Si NCs. Using ion beam synthesis, Si NCs can be fabricated along with standard CMOS processing. The optimization of the location and size of ion beam synthesized Si NCs requires a deeper understanding of the mechanisms involved, which determine (i) the built-up of Si supersaturation by high-fluence ion implantation and (ii) NC formation by phase separation. For that aim, process simulations have been conducted that address both aspects on a fundamental level and, on the other hand, are able to avoid tedious experiments. The built-up of a Si supersaturation by high-fluence ion implantation were studied using dynamic binary collision calculations with TRIDYN and have lead to a prediction of Si excess depth profiles in thin gate oxides of a remarkable quality. These simulations include in a natural manner high fluence implantation effects as target erosion by sputtering, target swelling and ion beam mixing. The second stage of ion beam synthesis is modeled with the help of a tailored kinetic Monte Carlo code that combines a detailed kinetic description of phase separation on atomic level with the required degree of abstraction that is necessary to span the timescales involved. Large ensembles of Si NCs were simulated reaching the late stages of NC formation and dissolution at simulation sizes that allowed a direct comparison with experimental studies, e.g. with electron energy loss resolved TEM investigations. These comparisons reveal a nice degree of agreement, e.g. in terms of predicted and observed precipitate morphologies for different ion fluences. However, they also point clearly onto impact of additional external influences as, e.g., the oxidation of implanted Si by absorbed humidity, which was identified with the help of these process simulations. Moreover, these simulations are utilized as a general tool to identify optimum processing regimes for a tailored Si NC formation for NC memories. It is shown that key properties for NC memories as the tunneling distance from the transistor channel to the Si NCs, the NC morphology, size and density can be adjusted accurately despite of the involved degree of self-organization. Furthermore, possible lateral electron tunneling between neighboring Si NCs is evaluated on the basis of the performed kinetic Monte Carlo simulations.

Metal-Oxide-Silicon Field-Effect-Transistors with a layer of electrically isolated Si nanocrystals (NCs) embedded in the gate oxide are known to improve conventional floating gate flash memories. Data retention, program and erase speeds as well as the memory operation voltages can be substantially improved due to the discrete charge storage in the isolated Si NCs. Using ion beam synthesis, Si NCs can be fabricated along with standard CMOS processing. The optimization of the location and size of ion beam synthesized Si NCs requires a deeper understanding of the mechanisms involved, which determine (i) the built-up of Si supersaturation by high-fluence ion implantation and (ii) NC formation by phase separation. For that aim, process simulations have been conducted that address both aspects on a fundamental level and, on the other hand, are able to avoid tedious experiments. The built-up of a Si supersaturation by high-fluence ion implantation were studied using dynamic binary collision calculations with TRIDYN and have lead to a prediction of Si excess depth profiles in thin gate oxides of a remarkable quality. These simulations include in a natural manner high fluence implantation effects as target erosion by sputtering, target swelling and ion beam mixing. The second stage of ion beam synthesis is modeled with the help of a tailored kinetic Monte Carlo code that combines a detailed kinetic description of phase separation on atomic level with the required degree of abstraction that is necessary to span the timescales involved. Large ensembles of Si NCs were simulated reaching the late stages of NC formation and dissolution at simulation sizes that allowed a direct comparison with experimental studies, e.g. with electron energy loss resolved TEM investigations. These comparisons reveal a nice degree of agreement, e.g. in terms of predicted and observed precipitate morphologies for different ion fluences. However, they also point clearly onto impact of additional external influences as, e.g., the oxidation of implanted Si by absorbed humidity, which was identified with the help of these process simulations. Moreover, these simulations are utilized as a general tool to identify optimum processing regimes for a tailored Si NC formation for NC memories. It is shown that key properties for NC memories as the tunneling distance from the transistor channel to the Si NCs, the NC morphology, size and density can be adjusted accurately despite of the involved degree of self-organization. Furthermore, possible lateral electron tunneling between neighboring Si NCs is evaluated on the basis of the performed kinetic Monte Carlo simulations.