Made available in DSpace on 2014-06-12T15:53:32Z (GMT). No. of bitstreams: 2 arquivo5149_1.pdf: 3970263 bytes, checksum: 9d5eb7ba6122760de6e5e455fb706f21 (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2005 / Bactérias do gênero Yersinia possuem um sistema de secreção tipo III, responsável pela translocação de fatores protéicos conhecidos como Yops, para o interior de células eucarióticas do hospedeiro. A proteína YopH é uma tirosina fosfatase que atua desfosforilando moléculas sinalizadoras e impedindo a fagocitose em macrófagos. Para uma secreção eficiente, ela necessita da presença da chaperona SycH que permite o seu reconhecimento pela maquinaria de secreção. Com a finalidade de analisar a expressão da proteína YopH em E. coli, foi construído um promotor híbrido formado pelo promotor lac de Escherichia coli seguido do promotor yopH de Yersinia enterocolitica. Este promotor foi capaz de direcionar uma forte expressão da YopH, em E. coli, e uma síntese ótima de YopH foi observada com o aumento da temperatura (37oC) e em culturas em fase de crescimento. A expressão da YopH foi investigada em linhagens defectivas de E. coli para as proteínas homólogas às histonas, Hha e H-NS. A expressão foi significantemente maior a 24oC que a 37oC, na ausência de H-NS, mas não na ausência de Hha. Estes resultados são compatíveis com o papel da H-NS na regulação da atividade do promotor yoph, possivelmente através da presença de curvas em sua estrutura. Para determinar se a presença da chaperona SycH influenciaria na expressão da YopH, em E. coli, a sequência codificadora para esta proteína foi amplificada e clonada no plasmídio pBAD33. Foi observada a expressão da SycH em culturas de E. coli, apenas na presença de arabinose. A co-expressão das proteínas YopH e SycH, em EPEC, revelou uma redução na expressão da YopH, na presença de arabinose. O mesmo foi observado em culturas de EPEC contendo apenas o plasmídio pTZ/YopH, onde concentrações variadas de arabinose e glicose estariam influenciando a expressão da YopH. Para verificar o potencial da proteína YopH no diagnóstico da peste, diversos soros de pacientes suspeitos de peste e coelhos imunizados com Y. pestis foram testados por Western-blot. Não houve reconhecimento da YopH nos soros testados

This diploma thesis focuses on the MANET Network (Mobile Ad-Hoc Network). There are theoretically elaborated basic information, the characteristics of the MANET network and great emphasis is placed on routing in these networks. In the next chapter the diploma thesis focuses on the Ad Hoc Demand Distance Vector (AODV) routing protocol. It features the characteristics of this protocol and the principle of communication and routing in MANET networks. Hereinafter, the individual reports of the AODV protocol are described in detail. In the third chapter, the thesis introduces the NS-3 simulation environment (network Simulator - 3) and then deals with the design of the MANET network in NS-3 using the AODV routing protocol. The practical part of the diploma thesis is the MANET network simulation and testing with the AODV routing protocol. Laboratory task is built from these simulations and the results of the testing.

An ad hoc mobile network is a collection of mobile nodes that are dynamically and arbitrarily located in such a manner that the interconnections between nodes are capable of changing on a continual basis. In order to simplify communication within the network, a routing protocol is used to discover routes between nodes. The primary goal of such an ad hoc network routing protocol is correct and efficient route establishment between a pair of nodes so that messages may be delivered on time. Route construction should be done with a minimum of overhead and bandwidth consumption. This document describes the Optimized Link State Routing (OLSR) protocol for mobile ad hoc networks. The key concept used in the protocol is that of multipoint relays (MPRs). MPRs provide an efficient mechanism for flooding control traffic by reducing the number of transmissions required.

Russian wildrye (Psathyrostachys juncea Fisch. 2n=2x=14, NsNs) is an important forage grass and a potentially useful germplasm in wheat improvement. A standard C-banding karyotype of Ps. juncea has been developed based on the C-bands of chromosomes in geographically diverse materials. Although there are C-banding polymorph isms, the seven pairs of chromosomes can be distinguished from each other according to their basic banding patterns. Based on C-banded karyotype, one deletion-t ranslocation heterozygote, four primary trisomies, one double-deletion trisomic, and two tertiary trisomies were identified. These cytogenetic stocks will be useful in genetic studies of Russian wildrye. Genetic variations in Russian wildrye were analyzed at chromosomal, protein and DNA levels using C-banding, isozymes, and randomly amplified polymorphic DNA (RAPD) techniques, respectively. Due to the self-incompatibility in Russia wild rye, a high level of genetic diversity existed both within and among accessions. In general, accessions originated from the same or neighboring geographical areas showed closer genetic relationships. The results of various approaches for genetic variation analysis suggest that there are tremendous genetic variations in the Russian wild rye germplasm for the effective improvement of this forage grass. Some molecular markers were isolated and characterized in Russian wildrye using RAPD and cloning techniques. These markers may be useful in gene mapping, species identification, studies of evolutionary relationships, and transferring useful genes into cereal crops.

No description available.

Convex programming is used in wireless networks to optimize the sending or receiving rates of links or flows in a network. This kind of optimization problem is formulated into a rate allocation problem, where each node in the network will distributively solve the convex problem and all links or flows will converge to their optimal rate. The objective function and constraints of these problems are represented in a simplified model of contention, interference, and sending or receiving rates. The Partial Interference model is an optimal rate allocation model for use in wireless mesh networks that has been shown to be theoretically superior to other conceptual models. This paper compares the Partial Interference model to three other models of wireless networks using the ns-3 simulator to verify these claims. It discusses where the model works as expected, where the model fails to improve network utility, and the limitations inherent to its use.

Le génome des bactéries vivantes n’est pas une entité statique mais au contraire c’est quelque chose très dynamique évoluant avec le temps. Les bactéries évoluent en acquérant par transfert horizontal des gènes du matériel génétique. C’est le cas des EPEC qui ont acquis l’îlot LEE via ce mécanisme. La protéine H-NS joue un rôle important dans la reconnaissance de cet ADN étranger, dans la liaison à cet ADN et dans la répression de son expression quand ce n’est pas en profit du « fitness » de la bactérie. Comme résultat H-NS régule la majorité des gènes associés à la virulence chez les entérobactéries Salmonella, Yersinia et les EPEC. Les EPEC possèdent une protéine paralogue à H-NS et codée dans le premier opéron de leur îlot LEE, il s’agit de la protéine Ler. Une fois exprimée Ler induit l’expression des 4 opérons restant de la région parmi lesquels LEE5. Ler partage une grande homologie avec H-NS surtout au niveau de leurs domaines de reconnaissance de l’ADN. Malgré cette homologie H-NS réprime LEE5 tandis que Ler l’active. De plus si H-NS est un régulateur global agissant sur plus de 500 gènes chez E. coli Ler est une protéine spécifique qui ne va agir que sur un petit nombre de promoteurs tous impliqués dans la virulence L’étude qualitative et quantitative de l’interaction de H-NS et de Ler avec la région promotrice de LEE5 montre qu’elles partagent globalement les mêmes sites de fixation sur des régions étendues en amont et en aval du +1 de la transcription. Ces sites de fixation sont bien définis d’une dizaine de paires de bases. L’affinité de ces sites pour H-NS est variable. Trois sites de haute affinité pour H-NS ont été identifiés. La séquence de ces sites est similaire à celle du site consensus élaboré en étudiant le promoteur proU(Bouffartigues et al - 2007). Des différences dans l’interaction de ces deux protéines avec le promoteur LEE5 résident surtout autour du +1 et des boîtes -10 et -35. Il s’agit de la première étude comparant la fixation de H-NS et de Ler sur des régions étendues de ce promoteur dans le but d’expliquer la régulation différentielle de ces deux protéines paralogues. L’étude de l’expression de LEE5 in vivo nous a permis de proposer que le mécanisme essentiel d’action de Ler est dirigé contre la répression induite par H-NS et que le taux maximum d’expression du promoteur LEE5 wtobservé dans la souche mutante pour hnsen présence de Ler (en comparaison avec la souche double mutante où Ler est absente) n’est pas dû à une activation directe par Ler mais plutôt à une répression par StpA, sensible à la mutation des sites de haute affinité de H-NS. / The genes of the LEE5 operon of enteropathogenic E.coliencode for proteinsthat are essential for their virulence. Their expression istightlyregulated, with H-NS silencing the transcriptional expression of LEE5 while Ler, product of the first operon of thispathogenicityislandcancounteract the silencing of H-NS. We show that H-NS and Ler use the samebinding sites on the LEE5 promoterin vitro. However, around the transcription start site differences in DNA constraints are detectabledepending on the presence of H-NS or Ler. Modification of the central AT bases, characteristic of H-NS consensus binding sites, affect the binding of bothproteinsin vitro and the expression in vivo of the LEE5 promoter. Additionallywe show that an additionalrepressor, the H-NS homologue StpA, isimplicated in the LEE5 regulationleading to a new model of how Ler canrelieve the H-NS imposedrepression on the LEE5 promoter

Este estudo é uma análise de interfaces e protocolos de automação que possuem potencial para serem adotados como padrões em redes elétricas inteligentes em um futuro próximo. A fim de verificar a possibilidade de implementar a IEC 61850 em uma aplicação típica de redes deste tipo, é realizada uma simulação usando o software NS-2. Os resultados deste trabalho servirão de orientação para o dimensionamento de redes de automação baseadas em IEC 61850. / This study is an analysis of automation interfaces and protocols with the potential to be adopted as standards for smart grids in the near future. In order to verify the feasibility of implementing the IEC 61850 in a typical application of such grids, it is performed a simulation using NS-2 software. The results of this work will be an orientation to dimension automation networks based on IEC 61850.

Este estudo é uma análise de interfaces e protocolos de automação que possuem potencial para serem adotados como padrões em redes elétricas inteligentes em um futuro próximo. A fim de verificar a possibilidade de implementar a IEC 61850 em uma aplicação típica de redes deste tipo, é realizada uma simulação usando o software NS-2. Os resultados deste trabalho servirão de orientação para o dimensionamento de redes de automação baseadas em IEC 61850. / This study is an analysis of automation interfaces and protocols with the potential to be adopted as standards for smart grids in the near future. In order to verify the feasibility of implementing the IEC 61850 in a typical application of such grids, it is performed a simulation using NS-2 software. The results of this work will be an orientation to dimension automation networks based on IEC 61850.

Les codes correcteurs d'erreurs sont une composante essentielle de tout système de communication, capables d’assurer le transport fiable de l’information sur un canal de communication bruité. Les systèmes de communication de nouvelle génération devront faire face à une demande sans cesse croissante en termes de débit binaire, pouvant aller de 1 à plusieurs centaines de gigabits par seconde. Dans ce contexte, les codes LDPC (pour Low-Density Parity-Check, en anglais), sont reconnus comme une des solutions les mieux adaptées, en raison de la possibilité de paralléliser massivement leurs algorithmes de décodage et les architectures matérielles associées. Cependant, si l’utilisation d’architectures massivement parallèles permet en effet d’atteindre des débits très élevés, cette solution entraine également une augmentation significative du coût matériel.L’objectif de cette thèse est de proposer des implémentations matérielles de décodeurs LDPC très haut débit, en exploitant la robustesse des algorithmes de décodage par passage de messages aux imprécisions de calcul. L’intégration dans le décodage itératif de mécanismes de calcul imprécis, s’accompagne du développement de nouvelles approches d’optimisation du design en termes de coût, débit et capacité de correction.Pour ce faire, nous avons considéré l’optimisation conjointe de (i) le bloc de quantification qui fournit l'information à précision finie au décodeur, et (ii) les unités de traitement imprécis des données, pour la mise à jour des messages échangés pendant de processus de décodage. Ainsi, nous avons tout d’abord proposé un quantificateur à faible complexité, qui peut être optimisé par évolution de densité en fonction du code LDPC utilisé et capable d’approcher de très près les performances d’un quantificateur optimal. Le quantificateur proposé a été en outre optimisé et utilisé pour chacun des décodeurs imprécis proposés ensuite dans cette thèse.Nous avons ensuite proposé, analysé et implémenté plusieurs décodeurs LDPC imprécis. Les deux premiers décodeurs sont des versions imprécises du décodeur « Offset Min-Sum » (OMS) : la surestimation des messages des nœuds de contrôle est d’abord compensée par un simple effacement du bit de poids faible (« Partially OMS »), ensuite le coût matériel est d’avantage réduit en supprimant un signal spécifique (« Imprecise Partially OMS »). Les résultats d’implémentation sur cible FPGA montrent une réduction importante du coût matériel, tout en assurant une performance de décodage très proche du OMS, malgré l'imprécision introduite dans les unités de traitement.Nous avions ensuite introduit les décodeurs à alphabet fini non-surjectifs (NS-FAIDs, pour « Non-Surjective Finite Alphabet Iterative Decoders », en anglais), qui étendent le concept d’« imprécision » au bloc mémoire du décodeur LDPC. Les décodeurs NS-FAIDs ont été optimisés par évolution de densité pour des codes LDPC réguliers et irréguliers. Les résultats d'optimisation révèlent différents compromis possibles entre la performance de décodage et l'efficacité de la mise en œuvre matérielle. Nous avons également proposé trois architectures matérielles haut débit, intégrant les noyaux de décodage NS-FAID. Les résultats d’implémentation sur cible FPGA et ASIC montrent que les NS-FAIDs permettent d’obtenir des améliorations significatives en termes de coût matériel et de débit, par rapport au décodeur Min-Sum, avec des performances de décodage meilleures ou très légèrement dégradées. / The increasing demand of massive data rates in wireless communication systems will require significantly higher processing speed of the baseband signal, as compared to conventional solutions. This is especially challenging for Forward Error Correction (FEC) mechanisms, since FEC decoding is one of the most computationally intensive baseband processing tasks, consuming a large amount of hardware resources and energy. The conventional approach to increase throughput is to use massively parallel architectures. In this context, Low-Density Parity-Check (LDPC) codes are recognized as the foremost solution, due to the intrinsic capacity of their decoders to accommodate various degrees of parallelism. They have found extensive applications in modern communication systems, due to their excellent decoding performance, high throughput capabilities, and power efficiency, and have been adopted in several recent communication standards.This thesis focuses on cost-effective, high-throughput hardware implementations of LDPC decoders, through exploiting the robustness of message-passing decoding algorithms to computing inaccuracies. It aims at providing new approaches to cost/throughput optimizations, through the use of imprecise computing and storage mechanisms, without jeopardizing the error correction performance of the LDPC code. To do so, imprecise processing within the iterative message-passing decoder is considered in conjunction with the quantization process that provides the finite-precision information to the decoder. Thus, we first investigate a low complexity code and decoder aware quantizer, which is shown to closely approach the performance of the quantizer with decision levels optimized through exhaustive search, and then propose several imprecise designs of Min-Sum (MS)-based decoders. Proposed imprecise designs are aimed at reducing the size of the memory and interconnect blocks, which are known to dominate the overall area/delay performance of the hardware design. Several approaches are proposed, which allow storing the exchanged messages using a lower precision than that used by the processing units, thus facilitating significant reductions of the memory and interconnect blocks, with even better or only slight degradation of the error correction performance.We propose two new decoding algorithms and hardware implementations, obtained by introducing two levels of impreciseness in the Offset MS (OMS) decoding: the Partially OMS (POMS), which performs only partially the offset correction, and the Imprecise Partially OMS (I-POMS), which introduces a further level of impreciseness in the check-node processing unit. FPGA implementation results show that they can achieve significant throughput increase with respect to the OMS, while providing very close decoding performance, despite the impreciseness introduced in the processing units.We further introduce a new approach for hardware efficient LDPC decoder design, referred to as Non-Surjective Finite-Alphabet Iterative Decoders (FAIDs). NS-FAIDs are optimized by Density Evolution for regular and irregular LDPC codes. Optimization results reveal different possible trade-offs between decoding performance and hardware implementation efficiency. To validate the promises of optimized NS-FAIDs in terms of hardware implementation benefits, we propose three high-throughput hardware architectures, integrating NS-FAIDs decoding kernels. Implementation results on both FPGA and ASIC technology show that NS-FAIDs allow significant improvements in terms of both throughput and hardware resources consumption, as compared to the Min-Sum decoder, with even better or only slightly degraded decoding performance.