Small-signal stability is of great concern for distributed power systems with a large number of regulated power converters. These converters are constant-power loads (CPLs) exhibit a negative incremental input resistance within the output voltage regulation bandwidth. In the case of dc systems, design requirements for impedances that guarantee stability have been previously developed and are used in the design and specification of these systems. In terms of three-phase ac systems, a mathematical framework based on the generalized Nyquist stability criterion (GNC), reference frame theory, and multivariable control is set forth for stability assessment. However, this approach relies on the actual measurement of these impedances, which up to now has severely hindered its applicability. Addressing this shortcoming, this research investigates the small-signal stability of three-phase ac systems using measured d-q frame impedances. Prior to this research, negative incremental resistance is only found in CPLs as a results of output voltage regulation. In this research, negative incremental resistance is discovered in grid-tied inverters as a consequence of grid synchronization and current injection, where the bandwidth of the phase-locked loop determines the frequency range of the negative incremental resistance behavior, and the power rating of inverter determines the magnitude of the resistance. Prior to this research, grid synchronization stability issue and sub-synchronous oscillations between grid-tied inverter and its nearby rectifier under weak grid condition are reported and analyzed using characteristic equation of the system. This research proposes a more design oriented analysis approach based on the negative incremental resistance concept of grid-tied inverters. Grid synchronization stability issues are well explained under the framework of GNC. Although stability and its margin of ac system can be addressed using source and load impedances in d-q frame, method to specify the shape of load impedances to assure system stability is not reported. This research finds out that under unity power factor condition, three-phase ac system is decoupled. It can be simplified to two dc systems. Load impedances can be then specified to guarantee system stability and less conservative design. / Ph. D.

Recently, the environmental impact of aircraft and rising fuel prices have become an increasing concern in the aviation industry. To address these problems, organizations such as NASA have set demanding goals for reducing aircraft emissions, fuel burn, and noise. In an effort to reach the goals, a movement toward more-electric aircraft and electric propulsion has emerged. With this movement, the number of critical electrical loads on an aircraft is increasing causing power system reliability to be a point of concern. Currently, power system reliability is maintained through the use of back-up power supplies such as batteries and ram-air-turbines (RATs). However, the increasing power requirements for critical loads will quickly outgrow the capacity of the emergency devices. Therefore, reliability needs to be addressed when designing the primary power distribution system. Power system reliability is a function of component reliability and redundancy. Component reliability is often not determined until detailed component design has occurred; however, the amount of redundancy in the system is often set during the system architecting phase. In order to meet the capacity and reliability requirements of future power distribution systems, a method for redundancy allocation during the system architecting phase is needed. This thesis presents an aircraft power system design methodology that is based upon the engineering decision process. The methodology provides a redundancy allocation strategy and quantitative trade-off environment to compare architecture and technology combinations based upon system capacity, weight, and reliability criteria. The methodology is demonstrated by architecting the power distribution system of an aircraft using turboelectric propulsion. The first step in the process is determining the design criteria which includes a 40 MW capacity requirement, a 20 MW capacity requirement for the an engine-out scenario, and a maximum catastrophic failure rate of one failure per billion flight hours. The next step is determining gaps between the performance of current power distribution systems and the requirements of the turboelectric system. A baseline architecture is analyzed by sizing the system using the turboelectric system power requirements and by calculating reliability using a stochastic flow network. To overcome the deficiencies discovered, new technologies and architectures are considered. Global optimization methods are used to find technology and architecture combinations that meet the system objectives and requirements. Lastly, a dynamic modeling environment is constructed to study the performance and stability of the candidate architectures. The combination of the optimization process and dynamic modeling facilitates the selection of a power system architecture that meets the system requirements and objectives.

Ultra narrow-band filters and the use of two loops in a cascade configuration dominate current clock conditioners based on phase-locked-loop (PLL) schemes. Since a PLL exhibits a low-pass transfer function with respect to the reference clock, the noise performance at very close-to-carrier offset frequencies is still determined by the input signal. Although better cleaning can be achieved with extremely narrow loops, an ultra low cut-off frequency could not be selected since the stability of the configuration deteriorates as the filter bandwidth is reduced. This fact suggests that a full-spectrum clock conditioning is not possible using traditional PLL architectures, and an alternative scheme is necessary to attenuate the very-close-to-carrier phase noise (PN). In addition, ultra-narrow loop filters can compromise on-chip integration because of the large size capacitors needed when chosen as passive. Input signal attenuation with relaxed bandwidth requirements becomes the main aspect that a comprehensive clock cleaner must address to effectively regenerate a reference signal. This dissertation describes the Band-Reject Nested-PLL (BRN-PLL) scheme, a modified PLL-based architecture that provides an effective signal cleaning procedure by introducing a notch in the input transfer function through inner and outer loops and a high-pass filter (HPF). This modified response attenuates the reference-signal PN and reduces the size of the loop-filter capacitors substantially. Ultra narrow loops are no longer required because the notch size is related to the system bandwidth. The associated transfer function for the constitutive blocks (phase detectors and local oscillators) show that the output close-to-carrier and far-from-carrier PN sections are mainly dominated by the noise from the inner-PLL phase detector (PD) and local oscillator (LO) located in the outer loop, respectively. The inner-PLL PD transfer function maintains a low-pass characteristic with a passband gain inversely proportional to the PD gain becoming the main contribution around the carrier signal. On the other hand, the PN around the transition frequency is determined mainly by the reference and the inner-PLL LO. Their noise contributions to the output will depend on the associated passband local maxima, which is located at the BRN-PLL transition frequency. Hence, in this region, the inner-PLL LO is selected so that its effect can be held below that of the outer-PLL PD. The BRN-PLL can use a high-Q MEMS-based VCO to further improve the transition region of the output PN profile and an LC-VCO as outer-PLL LO to reduce the noise floor of the output signal. In particular, two tuning mechanisms are explored for the MEMS-VCO: series tuning using varactors and phase shifting of a resonator operating in nonlinear regime. Both schemes are implemented to generate a tunable oscillator with no PN-performance degradation.