ITC/USA 2012 Conference Proceedings / The Forty-Eighth Annual International Telemetering Conference and Technical Exhibition / October 22-25, 2012 / Town and Country Resort & Convention Center, San Diego, California / As data transport systems become exponentially larger and more complex, the need to simplify the level of user involvement in establishing the intercommunication pathways becomes increasingly vital to streamlined, effective mission management. The proliferation of open-architecture, modular approaches to data transport and multiplexing systems shows the need for a unified, high-level control scheme that helps to flatten the users' learning curve for increasingly sophisticated, expanding systems. Implementing a control package with the functionality described in this paper will improve the user experience by eliminating the need for low level hardware management, minimizing system network footprint and unifying this functionality for a diverse hardware package.

This is a report concerning the body of artwork I have formulated in the last two of my three years spent as a graduate student in the M.F.A. program at the University of Texas at Austin. It provides a chronological description of key works and the influences drawn upon within this time frame. Broken into eight substantive sections, the report reflects an in-depth study on “object-hood.” / text

The purpose of this research was to investigate object classification algorithms for the application of wheelchair interaction with the environment for the cognitively impaired wheelchair user. Towards this end, top performing object classification algorithms were trained on images of the target object classes (chair, dresser, and sink/washbasin) obtained from the internet and tested on images of the target object classes obtain in the home and patient room environments; these algorithms were Locality-constrained Linear Coding (LLC) [1], Kernel Descriptors (KDES) [2], and Hierarchical Matching Pursuit (HMP) [3]. It was found that HMP achieved the highest over classification accuracy (71.3%) in the home environment and LLC achieved the greatest accuracy (85.0%) in the patient room environment. This research also sought to investigate the potential of active learning to improve upon the obtained classification performance. A maximum mean classification accuracy of 98.6% was achieved when active learning was applied.

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The purpose of this research was to investigate object classification algorithms for the application of wheelchair interaction with the environment for the cognitively impaired wheelchair user. Towards this end, top performing object classification algorithms were trained on images of the target object classes (chair, dresser, and sink/washbasin) obtained from the internet and tested on images of the target object classes obtain in the home and patient room environments; these algorithms were Locality-constrained Linear Coding (LLC) [1], Kernel Descriptors (KDES) [2], and Hierarchical Matching Pursuit (HMP) [3]. It was found that HMP achieved the highest over classification accuracy (71.3%) in the home environment and LLC achieved the greatest accuracy (85.0%) in the patient room environment. This research also sought to investigate the potential of active learning to improve upon the obtained classification performance. A maximum mean classification accuracy of 98.6% was achieved when active learning was applied.

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We propose a scalable and fexible hardware architecture for the extraction of image features, used in conjunction with an attentional cascade classifier for appearance-based object detection. Individual feature processors calculate feature-values in parallel, using parameter-sets and image data that is distributed via BRAM buffers. This approach can provide high utilization- and throughput-rates for a cascade classifier. Unlike previous hardware implementations, we are able to flexibly assign feature processors to either work on a single- or multiple image windows in parallel, depending on the complexity of the current cascade stage. The core of the architecture was implemented in the form of a streaming based FPGA design, and validated in simulation, synthesis, as well as via the use of a Logic Analyser for the verification of the on-chip functionality. For the given implementation, we focused on the design of Haar-like feature processors, but feature processors for a variety of heterogenous feature types, such as Gabor-like features, can also be accomodated by the proposed hardware architecture.