This thesis presents a bio-signal recording system with offset cancellation and a low power comparator. The recording of bio-signal requires high-gain amplification before recording, to match the input to the range of the analog to digital converter (ADC); interference could be a problem if it causes the amplifier to reach saturation, leaving the recording inoperable (i.e., blank) until it returns to its normal state. The proposed system can monitor the amplifier output, and reset the amplifier output to a point near the center of its dynamic range before the amplifier output leaves its dynamic range. The proposed system provides discrete compensation voltages to cancel the offset voltage, and thereby avoids the shortcomings of conventional filters. Furthermore, a low power and low offset voltage comparator for low current operation is proposed. It is suitable for the clock controller in a sampled bio-signal acquisition system. The measured current consumption of the comparator is less than 130 nA, and the offset voltage is 2 mV. The proposed recording system and comparator have been implemented in the TSMC (Taiwan Semiconductor Manufacturing Company) 0.35£gm 2P4M CMOS process technology to verify the simulation results as well as the correctness of the proposed architecture.

Indiana University-Purdue University Indianapolis (IUPUI) / The nanotechnology materials have been used for high sensitivity sensing devices due to their ability to alter their properties in response to the environmental parameters such as temperature, pressure, gas, electromagnetic, and chemicals. The features of employing nanoparticles on top of graphene thin film have driven the hypothesis of achieving high sensing nanotechnology devices. This study demonstrates a novel approach for designing a low noise nanoparticle based gas sensing device with internet of things (IoT) capability. The system is capable of minimizing cross-talk between multiple channels of amplifiers arranged on one chip using guard rings. Graphene mono-layer is utilized as sensing material with the sensitivity catalyzed by addition of gold nano-particles on its surface. The signal from the sensing unit is received by an offset cancellation amplifying system using a system on chip (SoC) approach. IoT capability of the sensing device is developed using FRDM K64f micro-controller board which sends messages on IoT platform when a gas is sensed. The message is received by an application created and sent as an email or message to the user. This study details the mathematical models of the graphene based gas sensing devices, and the interface circuitry that drives the differential potentials, resulting from the sensing unit. The study presents the simulation and practical model of the device, detailing the design approach of the processing unit within the SoC system and wireless implementation of it. The sensing device was capable of sensing gas concentration from 5% to 100% using both the resistive and capacitive based models. The I-V characteristics of the FET sensing device was in agreeable with the other models. The SoC processing unit was designed using cadence tools, and simulation results showed very high CMRR that enable the amplifier to sense a very low signal received from the gas sensors. The cross talk noise was reduced by surrounding guard rings around the amplifier circuits. The layout was accomplished with 45nm technology and simulation showed an offset voltage of 17μV.

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Soft errors are radiation-induced ionization events (induced by energetic particles like alpha particles, cosmic neutron, etc.) that cause transient errors in integrated circuits. The circuit can always recover from such errors as the underlying semiconductor material is not damaged and hence, they are called soft errors. In nanometer technologies, the reduced node capacitance and supply voltage coupled with high packing density and lack of masking mechanisms are primarily responsible for the increased susceptibility of SRAMs towards soft errors. Coupled with these are the process variations (effective length, width, and threshold voltage), which are prominent in scaled-down technologies. Typically, SRAM constitutes up to 90% of the die in microprocessors and SoCs (System-on-Chip). Hence, the soft errors in SRAMs pose a potential threat to the reliable operation of the system. In this work, a soft-error-robust eight-transistor SRAM cell (8T) is proposed to establish a balance between low power consumption and soft error robustness. Using metrics like access time, leakage power, and sensitivity to single event transients (SET), the proposed approach is evaluated. For the purpose of analysis and comparisons the results of 8T cell are compared with a standard 6T SRAM cell and the state-of-the-art soft-error-robust SRAM cells. Based on simulation results in a 65-nm commercial CMOS process, the 8T cell demonstrates higher immunity to SETs along with smaller area and comparable leakage power. A 32-kb array of 8T cells was fabricated in silicon. After functional verification of the test chip, a radiation test was conducted to evaluate the soft error robustness. As SRAM cells are scaled aggressively to increase the overall packing density, the smaller transistors exhibit higher degrees of process variation and mismatch, leading to larger offset voltages. For SRAM sense amplifiers, higher offset voltages lead to an increased likelihood of an incorrect decision. To address this issue, a sense amplifier capable of cancelling the input offset voltage is presented. The simulated and measured results in 180-nm technology show that the sense amplifier is capable of detecting a 4 mV differential input signal under dc and transient conditions. The proposed sense amplifier, when compared with a conventional sense amplifier, has a similar die area and a greatly reduced offset voltage. Additionally, a dual-input sense amplifier architecture is proposed with corroborating silicon results to show that it requires smaller differential input to evaluate correctly.

In this work, programmable analog techniques using floating-gate transistors have been developed to design precision analog circuits, low-power signal processing primitives and adaptive systems that learn on-chip. Traditional analog implementations lack programmability with the result that issues such as mismatch are corrected at the expense of area. Techniques have been proposed that use floating-gate transistors as an integral part of the circuit of interest to provide both programmability and the ability to correct for mismatch. Traditionally, signal processing has been performed in the digital domain with analog circuits handling the interface with the outside world. Such a partitioning of responsibilities is inefficient as signal processing involves repeated multiplication and addition operations that are both very power efficient in the analog domain. Using programmable analog techniques, fundamental signal processing primitives such as multipliers have been developed in a low-power fashion while preserving accuracy. This results in a paradigm shift in signal processing. A co-operative analog/digital signal processing framework is now possible such that the partitioning of tasks between the analog and digital domains is performed in a power efficient manner. Complex signal processing tasks such as adaptive filtering that learn the weight coefficients are implemented by exploiting the non-linearities inherent with floating-gate programming. The resulting floating-gate synapses are compact, low-power and offer the benefits of non-volatile weight storage. In summary, this research involves developing techniques for improving analog circuit performance and in developing power-efficient techniques for signal processing and on-chip learning.