Today nucleate boiling is widely used in numerous industrial applications such as cooling processes because of the high achieved heat transfer rates for low temperature differences. It remains a possible cooling solution for the next generation of central processing units (CPU), which dissipate heat fluxes exceeding the capabilities of today’s conventional forced air cooling. However, nucleate boiling is a very complex and elusive process involving many mechanisms which are not fully understood yet and a comprehensive model is still missing. For this study a new experimental setup was designed, constructed and commissioned to investigate bubble nucleation, growth, departure and interaction during nucleate pool boiling from a silicon device fully immersed in fluorinert FC-72. The location of bubble nucleation is controlled by artificial cavities etched into the silicon substrate. Boiling is initiated with a heater integrated on the back and micro-sensors indicate the wall temperature at the bubble nucleation site. During this work three different silicon test section designs were fabricated and boiling experiments on these substrates successfully conducted. Bubble growth, bubble departure frequencies and bubble departure diameters for different dimensioned artificial cavities, varied pressure and increasing wall temperature were measured from high-speed imaging sequences. Bubble interactions like vertical and horizontal coalescence were visualised and their impact on the boiling heat transfer investigated. The influence of spacing between two neighbouring artificial cavities on bubble nucleation and departure frequencies, vertical coalescence frequencies and departure diameters was analysed. The acquired data are used as input for a numerical code developed by our collaborators (Brunel University, UK and Los Alamos National Laboratories, USA) and are a first step to validate the code. The code studies the interactions between bubble nucleation sites on solid surfaces as a network. The simulations will help design boiling substrates utilised for chip cooling applications with optimal artificial cavity distribution to maximise the cooling heat transfer.

Mémoire numérisé par la Direction des bibliothèques de l'Université de Montréal.

Supersymmetry is a theoretical model of particle physics that posits a symmetry between bosons and fermions. Supersymmetry proposes the existence of particles that we have not yet observed and through them, offers a more unified view of the universe. In the same way Feynman Diagrams represent Feynman Integrals describing subatomic particle behaviour, supersymmetry algebras can be represented by graphs called adinkras. In addition to being motivated by physics, these graphs are highly structured and mathematically interesting. No one has looked at the Jacobians of these graphs before, so we attempt to characterize them in this thesis. We compute Jacobians through the 11-cube, but do not discover any significant discernible patterns. We then dedicate the rest of our work to generalizing the notion of the Jacobian, specifically to be sensitive to edge directions. We conclude with a conjecture describing the form of the directed Jacobian of the directed $n$-topology. We hope for this work to be useful for theoretical particle physics and for graph theory in general.

Mémoire numérisé par la Direction des bibliothèques de l'Université de Montréal.

A system-on-chip (SoC) with near-threshold supply voltage (NTV) operation has received a significant amount of attention. Its high energy-efficiency supports a number of low-power emerging applications such as wireless sensor networks and Internet-of-Thing edge devices. Integrating various digital, analog, mixed-signal, and power sub-systems, such SoC designs need to employ tens of voltage domains to push the envelope of energy-efficiency, performance, and robustness. A low-drop-out (LDO) regulator is a key building block for creating voltage domains on a chip thanks to its high power density. In particular, its digital implementation, i.e., digital LDO, recently has emerged as a popular topology since it can support a wide range of input voltage from super-threshold to near-threshold voltage regimes, while conventional analog LDOs become less effective. One of the critical overheads in existing digital LDO designs is a requirement of off-chip output capacitor for stabilizing the output voltage, due to inadequate latency in active control paths. It is possible to employ higher clock frequency in a digital LDO; however such solutions inevitably increase power dissipation. This off-chip capacitor overhead can significantly increase chip pin count and printed circuit board (PCB) space, thus limiting the number of power domains that an SoC can have. This thesis presents my research on fully-integrated digital LDO designs based on event-driven control architecture. My research focuses on scaling down the output capacitor size to the integrable level and improving transient performance such as maximum voltage change and settling time. To shrink the output capacitor size, we introduced the event-driven control and the binary digital PI controller in our first event-driven LDO design. Thanks to the event-driven control, we achieved control loop latency reduction without compromising power consumption, leading to output capacitor size reduction. The first design shows 2.7x improvement over the previous digital LDO designs in Figure-of-Merit with a 400pF of output capacitor. To further reduce output capacitor size and support larger load current, we implemented the second event-driven digital LDO designs with fine-grained parallelism. The parallel structure of its PI controller reduces the latency of the proportional part, which mainly regulates output voltage, so it achieves better transient performance with reduced size of capacitor. Also, the parallel-shift-register-based integration part lowers computation and area overheads. The second design outperforms the state of the arts by over 17x in Figure-of-Merits with only a 100pF of output capacitor. In the last design, we introduced initialization and self-triggering control. The initialization estimates load current change in the beginning of regulation process and sets the controller output close to the desired value. This leads to substantial reduction of settling time. Also, thanks to self-triggering control, the hardware overhead from counting the event interval is removed without the first response time degradation, achieving high current density. The last design with a 100pF of output capacitor improves settling time and current density by 3.8x and 6.7x, respectively, while achieving comparable transient performance in terms of Figure-of-Merit.

With the number of transistors integrated into a single integrated circuit (IC) crossing the one-billion mark and complementary metal-oxide-semiconductor (CMOS) technology scaling pushing device dimensions ever-so-close to atomic scales, variability in transistor performance is becoming the dominant constraint in modern-day CMOS IC design. Developing novel approaches for device characterization, which allow a detailed study of electrical transistor characteristics across large statistical sample sets, is crucial for the proper identification, characterization, and modeling of different physical sources of device variability. On-chip characterization methodologies have the potential to address all of these issues by enabling the characterization of large statistical device sample sets, while also allowing for high measurement quality and throughput. In this work, a fully-integrated system for on-chip combined capacitance-voltage (C-V) and current-voltage (I-V) characterization of a large integrated test transistor array implemented in a 45-nm bulk CMOS process is presented. On-chip I-V characterization is implemented using a four-point Kelvin measurement technique with 12-bit sub-10 nA current measurement resolution, 10-bit sub-1 mV voltage measurement resolution, and sampling speeds on the order of 100 kHz. C-V characterization is performed using a novel leakage- and parasitics-insensitive charge-based capacitance measurement (CBCM) technique with atto-Farad resolution. The on-chip system is employed in developing a comprehensive CMOS transistor variability characterization methodology, studying both random and systematic sources of quasi-static device variability. For the first time, combined C-V/I-V characterization of circuit-representative devices is demonstrated and used to extract variations in the under- lying physical parameters of the device. Additionally, the fast current sampling capabilities of the system are used for the characterization of random telegraph noise (RTN) in small area devices. An automated methodology for the extraction of RTN parameters is developed, and the statistics of RTN are studied across device type, bias, and geometry.

In this era of exascale computing, conventional synchronous design techniques are facing unprecedented challenges. The consumer electronics market is replete with many-core systems in the range of 16 cores to thousands of cores on chip, integrating multi-billion transistors. However, with this ever increasing complexity, the traditional design approaches are facing key issues such as increasing chip power, process variability, aging, thermal problems, and scalability. An alternative paradigm that has gained significant interest in the last decade is asynchronous design. Asynchronous designs have several potential advantages: they are naturally energy proportional, burning power only when active, do not require complex clock distribution, are robust to different forms of variability, and provide ease of composability for heterogeneous platforms. Networks-on-chip (NoCs) is an interconnect paradigm that has been introduced to deal with the ever-increasing system complexity. NoCs provide a distributed, scalable, and efficient interconnect solution for today’s many-core systems. Moreover, NoCs are a natural match with asynchronous design techniques, as they separate communication infrastructure and timing from the computational elements. To this end, globally-asynchronous locally-synchronous (GALS) systems that interconnect multiple processing cores, operating at different clock speeds, using an asynchronous NoC, have gained significant interest. While asynchronous NoCs have several advantages, they also face a key challenge of supporting new types of traffic patterns. Once such pattern is multicast communication, where a source sends packets to arbitrary number of destinations. Multicast is not only common in parallel computing, such as for cache coherency, but also for emerging areas such as neuromorphic computing. This important capability has been largely missing from asynchronous NoCs. This thesis introduces several efficient multicast solutions for these interconnects. In particular, techniques, and network architectures are introduced to support high-performance and low-power multicast. Two leading network topologies are the focus: a variant mesh-of-trees (MoT) and a 2D mesh. In addition, for a more realistic implementation and analysis, as well as significantly advancing the field of asynchronous NoCs, this thesis also targets synthesis of these NoCs on commercial FPGAs. While there has been significant advances in FPGA technologies, there has been only limited research on implementing asynchronous NoCs on FPGAs. To this end, a systematic computeraided design (CAD) methodology has been introduced to efficiently and safely map asynchronous NoCs on FPGAs. Overall, this thesis makes the following three contributions. The first contribution is a multicast solution for a variant MoT network topology. This topology consists of simple low-radix switches, and has been used in high-performance computing platforms. A novel local speculation technique is introduced, where a subset of the network’s switches are speculative that always broadcast every packet. These switches are very simple and have high performance. Speculative switches are surrounded by non-speculative ones that route packets based on their destinations and also throttle any redundant copies created by the former. This hybrid network architecture achieved significant performance and power benefits over other multicast approaches. The second contribution is a multicast solution for a 2D-mesh topology, which is more complex with higher-radix switches and also is more commonly used. A novel continuous-time replication strategy is introduced to optimize the critical multi-way forking operation of a multicast transmission. In this technique, a multicast packet is first stored in an input port of a switch, from where it is sent through distinct output ports towards different destinations concurrently, at each output’s own rate and in continuous time. This strategy is shown to have significant latency and energy benefits over an approach that performs multicast using multiple distinct serial unicasts to each destination. Finally, a systematic CAD methodology is introduced to synthesize asynchronous NoCs on commercial FPGAs. A two-fold goal is targeted: correctness and high performance. For ease of implementation, only existing FPGA synthesis tools are used. Moreover, since asynchronous NoCs involve special asynchronous components, a comprehensive guide is introduced to map these elements correctly and efficiently. Two asynchronous NoC switches are synthesized using the proposed approach on a leading Xilinx FPGA in 28 nm: one that only handles unicast, and the other that also supports multicast. Both showed significant energy benefits with some performance gains over a state-of-the-art synchronous switch.

RA is a chronic and disabling disease with no known cure. The disease has a strong genetic component and modern genetic studies have successfully identified over 100 loci associated with the onset of RA. Despite the number of associations identified, the full genetic component of RA is not known, and for the majority of the loci the causal variant remains unknown. The overall aim of this study was to utilise well-powered genetic data, in order to identify novel loci, refine genetic associations, and generate robust evidence for the causal SNP and causal gene at a selected RA locus. An initial analysis was undertaken utilising 3870 RA cases and 8430 controls from the UK-ImmunoChip, a study designed for comprehensive fine-mapping of confirmed RA susceptibility loci. Analysis of the UK-ImmunoChip data identified a novel finding with the TYK2 locus, and proved informative to refining association signals, illustrating the utility of fine-mapping and implicated SNPs with putative regulatory function. The UK-ImmunoChip was subsequently expanded to incorporate samples from five additional cohorts in a study led by Dr. Stephen Eyre. In additional to novel loci discovery, this study provided evidence for SNPs putatively associated with RA (P smaller or equal to5E-05 < 5E-08). In a combined meta-analysis of 17,581 cases and 20,160 controls, convincing evidence was obtained for two novel RA loci, BACH2 and RAD51B.The newly identified genes implicate two novel pathways in RA (B-cell differentiation and DNA repair) and add to the growing number of loci associated with multiple AIDs. These findings are important to aid comprehensive pathway analysis and add to the knowledge of RA risk genes. The third most associated RA locus in both serological subtypes of disease, with an uncharacterised protein, ANKRD55, was subsequently selected for in-depth characterisation. Utilising genetic and haplotypic analysis the association at this locus was refined to a single signal, with four SNPs in strong LD (r2 > 0.8). Through bioinformatic analysis, two SNPs rs6859219 and rs10065637 showed evidence for functional activity, with evidence of being located in an enhancer element, supported by histone marks, DNAse hypersensitivity, evidence of transcription factor binding and eQTL. The use of RNA and ChIP experiments have established a testable hypothesis that the presence of the putative causal variants rs6859219 and rs10065637, act to weaken the strength of the enhancer element in which they are located, (evidenced by diminished H3k4me1 modification), which in turn down-regulates the transcriptional output of the target gene ANKRD55 (evidenced by eQTL in both whole blood and CD4+ T cells).In summary this study has led to the identification of three novel loci, highlighted the importance of fine-mapping and developed a successful systemic strategy for the characterisation of the 5q11 risk locus associated with RA.

Les microsystèmes intégrant des techniques microfluidiques offrent la possibilité de réaliser des analyses biologiques directement sur le site de prélèvement de l’échantillon. Ils ont pour objectifs notamment d’augmenter l’efficacité, la rapidité et l’accessibilité de ces tests. Pour développer efficacement un tel dispositif, un ensemble de critères doit être fixé tels que la limitation du coût, la portabilité, la simplicité d’utilisation et la précision des résultats. Un objectif de cette thèse est également de proposer un nouveau système portable permettant de répondre à un maximum d’applications. Pour cela, il convient d’intégrer et d’automatiser des protocoles biologiques complexes c’est-à-dire nécessitant l’ajout de plusieurs réactifs et des réactions en parallèle. A titre d’exemple, les tests ELISA sont abordés.Pour répondre à cette problématique, une technique innovante utilisant un matériau hyperélastique est combinée à une architecture X-Y. Des chambres étirables, permettant de calibrer et de mélanger des volumes compris entre 1 µL et une centaine de µL, sont ainsi réalisées. Différents protocoles sont intégrés et validés par ordre de complexité croissante dans des cartes microfluidiques en commençant par une gamme de dilution qui est la première étape pour la calibration des protocoles biologiques, puis un test enzymatique et un test ELISA homogène, avant d’aborder le test ELISA hétérogène qui est le protocole visé.Un démonstrateur permettant de piloter les cartes microfluidiques est ensuite présenté. Cette plateforme est générique et compatible avec les cartes microfluidiques développées. Enfin, pour automatiser complétement la mise en œuvre des protocoles, une nouvelle technique d’embarquement de réactifs liquide est proposée. / Microsystems utilizing microfluidic techniques offer the possibility to perform point-of-need biological analysis. An objective of these systems is to increase the efficiency, speed and accessibility of these analyses. In order to effectively develop this kind of device, a set of criteria must be established and adhered to. This set should address cost limitations, portability, user-friendliness, and accuracy of the results. Another objective is to propose a new portable system that has the capability to address as many applications as possible. To this end, complex biological assays with multiple steps and multiple reagents must be integrated and automated. ELISA is one such assay being considered.To deal with this issue, an innovative technique employs a hyper-elastic material joined to an X-Y architecture. The resulting chambers are flexible, thus allowing for calibration and mixing on the range of 1 µL to hundreds of µL. Several protocols are integrated and validated in microfluidic chips in order of increasing complexity. To start, a range of dilutions is performed, which is then used to calibrate biological assay. Next, an enzymatic assay and a homogeneous ELISA are integrated. Finally, heterogeneous ELISA, which is the aimed assay, is achieved.We present here a prototype to demonstrate the handling of the microfluidic chip. This platform is versatile and compatible with those that have been previously developed. Additionally, the introduction and integration of liquid reagents is proposed in order to completely automate the protocol.

Qian, Zaichen. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references (leaves 62-67). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- VLSI Design Methodology --- p.1 / Chapter 1.2 --- Low Power Design --- p.6 / Chapter 1.3 --- Literature Review on Multiple Supply Voltage (MSV) --- p.10 / Chapter 1.3.1 --- Voltage Island Partitioning Problems --- p.11 / Chapter 1.3.2 --- Multiple Voltage Assignment (MVA) Problem --- p.12 / Chapter 1.4 --- Literature Review on Dynamic Voltage Scaling and Dynamic Power Management --- p.15 / Chapter 1.4.1 --- Dynamic Voltage Scaling (DVS) Problem --- p.16 / Chapter 1.4.2 --- Dynamic Power Management --- p.20 / Chapter 1.5 --- Thesis Contribution and Organization --- p.22 / Chapter 2 --- Multi-Voltage Floorplan Design --- p.24 / Chapter 2.1 --- Introduction --- p.24 / Chapter 2.2 --- Problem Formulation --- p.26 / Chapter 2.3 --- A Value-Oriented Branch-and-Bound Algorithm --- p.29 / Chapter 2.3.1 --- Branching Rules --- p.30 / Chapter 2.3.2 --- Upper Bounds --- p.31 / Chapter 2.3.3 --- Lower Bounds --- p.32 / Chapter 2.3.4 --- Pruning Rules and Value-Oriented Searching Rules --- p.33 / Chapter 2.4 --- Floorplanning --- p.35 / Chapter 2.5 --- Experimental Results --- p.36 / Chapter 2.5.1 --- Optimal Voltage Assignment --- p.37 / Chapter 2.5.2 --- Floorplanning Results --- p.38 / Chapter 3 --- Low Power Scheduling at System Level --- p.40 / Chapter 3.1 --- Introduction --- p.40 / Chapter 3.2 --- Problem Formulation --- p.42 / Chapter 3.3 --- An Optimal Offline Algorithm --- p.43 / Chapter 3.4 --- Online Algorithm --- p.46 / Chapter 3.4.1 --- Analysis on One Single Interval --- p.46 / Chapter 3.4.2 --- Online Algorithm --- p.49 / Chapter 3.4.3 --- Analysis of the Online Algorithm --- p.52 / Chapter 3.5 --- Experimental Results --- p.56 / Chapter 4 --- Conclusion and Future Work --- p.60 / Bibliography --- p.67