Over the last two decades or so, metal matrix composites (MMCs) have been drawing the attention of the industry due to their potentials in fulfilling demands for high performance industrial materials, products and advanced engineering applications. On the other hand, the high precision machining is becoming one of the most effective methods for enabling these difficult-to-machine composites to be applied particularly in precision engineering. Therefore, in-depth scientific understanding of MMC precision machining is essential and much needed so as to fulfil the gap between fundamental issues in precision machining of MMCs and their industrial scale applications. This thesis focuses on development of a multiscale multiphysics based approach to investigating the machinability of particulate MMCs and the machining process optimisation. In order to investigate the surface generation in relation to the process variables, this PhD study covers the key fundamental issues including chip formation process, dynamic cutting force, cutting temperature partition and tool wear by means of combining modelling, simulation and experimental study. The chip formation mechanisms and the minimum chip thickness in precision machining of SiCp/Al and B4Cp/Al MMCs by using PCD tools are investigated through a holistic approach. Minimum chip thickness (MCT) value is firstly identified based on the modified mathematical model. The certain threshold of the uncut chip thickness, i.e. chips starting to form at this chip thickness point, is then established. The chip formation process including the matrix material breakage, particles fracture, debonding, sliding or removal and their interfacial interactions are further simulated using finite element analysis (FEA). The minimum chip thickness and chip formation simulations are evaluated and validated via well-designed experimental trials on a diamond turning machine. The chips and surface profiles formed under varied process variables in periodic material removals are inspected and measured in order to obtain a better understanding on MMC chip formation mechanisms. The improved dynamic cutting force model is developed based on the micro cutting mechanics involving the size effect, undeformed chip thickness effects and the influence of cutting parameters in the micro scale. Cutting process variables, particle form, size and volume fraction at different scales are taken into account in the modelling. The cutting force multiscale modelling is proposed to have a better understanding on the MMCs cutting mechanics and to predict the cutting force accurately. The cutting forces are modelled and analysed in three cutting regimes: elastic recovery zone, ploughing zone and shearing zone. A novel instantaneous chip thickness algorithm including real chip thickness and real tool trajectory is developed by taking account of the tool runout. Well-designed cutting trials are carried out under varied process variables to evaluate and validate the force model. In order to obtain the actual cutting forces accurately, transfer function technique is employed to compensate the measured cutting forces. The cutting force model is further applied to correlate the cutting tool wear and the prediction of the machined surface generation. Multiphysics coupled thermal-mechanical-tribological model and FE analysis are developed to investigate the cutting stress, cutting temperature, tool wear and their intrinsic relationships in MMCs precision machining process. Heat generation, heat transfer and cutting temperature partition in workpiece, chips and cutting tool are simulated. A modified tool wear rate model is proposed, tool wear characteristics, wear mechanisms and dominate tool wear are further investigated against the real machining process. Cutting tool wear is monitored and assessed offline after machining experiments. The experimental study on the machined surface generation is presented covering cutting force, tool wear, tool life, surface roughness and machining efficiency. Process optimisation is explored by considering the variation of cutting parameters, cutting tool conditions and workpiece materials in order to achieve the desired outcomes and machinability.

Traditionally, on-chip network communication was achieved with shared medium networks where devices shared the transmission medium with only one device driving the network at a time. To avoid performance losses, it required a fast bus arbitration logic. However, a single shared bus has serious limitations with the heterogeneous and multi-core communication requirements of today's chip designs. Point-to-point or direct networks solved some of the scalability issues, but the use of routers and of rather complex algorithms to connect nodes during each cycle caused new bottlenecks. As technology scales, the on-chip physical interconnect presents an increasingly limiting factor for performance and energy consumption. Network-on-chip, an emerging interconnect paradigm, provide solutions to these interconnect and communication challenges. Motivated by future bottom-up self-assembled fabrication techniques, which are believed to produce largely unstructured interconnect fabrics in a very inexpensive way, the goal of this thesis is to explore the design trade-offs of such irregular, heterogeneous, and unreliable networks. The important measures we care about for our complex on-chip network models are the information transfer, congestion avoidance, throughput, and latency. We use two control parameters and a network model inspired by Watts and Strogatz's small-world network model to generate a large class of different networks. We then evaluate their cost and performance and introduce a function which allows us to systematically explore the trade-offs between cost and performance depending on the designer's requirement. We further evaluate these networks under different traffic conditions and introduce an adaptive and topology-agnostic ant routing algorithm that does not require any global control and avoids network congestion.

Network-on-Chips (NoCs) have become the standard communication platform for future massively parallel systems due to their performance, flexibility and scalability advantages. However, reliability issues brought about by scaling in the sub-20nm era threaten to undermine the benefits offered by NoCs. This dissertation demonstrates design techniques that address both reliability and security issues facing modern NoC architectures. The reliability and security problem is tackled at different abstraction levels using a series of schemes that combine information from the architecture-level as well as hardware-level in order to combat aging effects and meet secure design stipulations while maintaining modest power-performance overheads.

This research utilizes Electrical Impedance Spectroscopy, a technique classically used for electrochemical analysis and material characterization, as the basis for a non-destructive, label-free assay platform for three dimensional (3D) cellular spheroids. In this work, a linear array of microelectrodes is optimized to rapidly respond to changes located within a 3D multicellular model. In addition, this technique is coupled with an on chip micro-pH sensor for monitoring the environment around the cells. Finally, the responses of both impedance and pH are correlated with physical changes within the cellular model. The impedance analysis system realized through this work provides a foundation for the development of high-throughput drug screening systems that utilize multiple parallel sensing modalities including pH and impedance sensing in order to quickly assess the efficacy of specific drug candidates. The slow development of new drugs is mainly attributed to poor predictability of current chemosensitivity and resistivity assays, as well as genetic differences between the animal models used for tests and humans. In addition, monolayer cultures used in early experimentation are fundamentally different from the complex structure of organs in vivo. This requires the study of smaller 3D models (spheroids) that more efficiently replicate the conditions within the body. The main objective of this research was to develop a microfluidic system on a chip that is capable of deducing viability and morphology of 3D tumor spheroids by monitoring both the impedance of the cellular model and the pH of their local environment. This would provide a fast and reliable method for screening pharmaceutical compounds in a high-throughput system.

Thesis (Ph.D.)--McMaster University, 2005. / Supervisor: Nicola Nicolici. Includes bibliographical references (189-208 p.)

<p>The computer engineering group at Linköping University has parts of their research dedicated to networks-on-chip and components used in network components and terminals. This research has among others resulted in the SoCBUS NOC and a flow based network protocol processor. The main objective of this project was to integrate these components into an IP router with two or more Gigabit Ethernet interfaces.</p><p>A working system has been designed and found working. It consists of three main components, the input module, the output module and a packet buffer. Due to the time constraint and the size of the project the packet buffer could not be designed to be as efficient as possible, thus reducing the overall performance. The SoCBUS also has negative impact on performance, although this could probably be reduced with a revised system design. If such a project is carried out it could use the input and output modules from this project, which connect to SoCBUS and can easily be integrated with other packet buffers and system designs.</p>

Most patients undergoing androgen deprivation therapy relapse eventually and progress to androgen-independent (AI) prostate cancer. Although the mechanisms underlying progression to AI prostate cancer are not well understood, studies suggest that androgen receptor (AR) is still required for AI prostate cancer. Our lab found that Vav3, a Rho GTPase guanine nucleotide exchange factor (GEF), is up-regulated during the progression of androgen-dependent human prostate cancer cells to androgen-independence in vivo and in cell-based experiments. Since Vav3 significantly increases ligand-dependent AR transcriptional activity and this action requires the Vav3 pleckstrin homology (PH) domain but not Vav3 GEF activity, we explored the role of the Vav3 PH domain in ligand-dependent AR coactivation by Vav3. We found that targeting the Vav3 PH mutant into nuclei but not the plasma membrane restored Vav3 PH mutant in AR coactivation. Targeting Vav3 to the plasma membrane eliminated the capacity of Vav3 to coactivate AR. In agreement with nuclear targeting of Vav3 via its PH domain, chromatin immunoprecipitation assays showed that Vav3 enhancement of AR transcriptional activity was accompanied by Vav3 recruitment to AR transcriptional complexes at an AR target gene enhancer. Further, Vav3 increased AR occupancy at the target gene enhancer upon androgen treatment and this may underlie the capacity of Vav3 to enhance AR transcriptional activity. Because Vav3 can also be activated by growth factors (GFs) and GFs activate AR in the absence of androgen (ligand-independent), we investigated the crosstalk between Vav3 and GF activation of AR and found Vav3 strongly enhanced AR transcriptional activity induced by GFs. GEF function and the downstream Rho GTPase, Rac1 were required for constitutively active (Ca) Vav3 activation of AR, which differs from Vav3 activation of AR in the presence of androgen. We also investigated the possible signal pathways contributing to AR activation by Ca Rac1. Ca Rac1 caused ligand-independent activation of AR in part through MAPK/ERK signaling and conferred prostate cancer growth in the absence of androgen in cell culture, soft agar and mouse tumor xenografts. Thus, our findings indicate that Vav3 activates AR in the presence or absence of ligand through two distinct mechanisms, which supports a versatile regulatory effect of Vav3 in AR signaling and prostate cancer progression.

The work presented in this thesis targets the analysis and implementation of multi-criteria performance prediction methods for System-on-Chips (SoC). These new SoC architectures offer the opportunity to integrate complete heterogeneous systems into a single chip and can be used to design battery powered handhelds, security critical systems, consumer electronics devices, etc. However, this variety in terms of application usually comes with a lot of different performance objectives like power consumption, yield, design cost, production cost, silicon area and many others. These performance requirements are often very difficult to meet together so that SoC design usually relies on making the right design choices and finding the best performance compromises. In parallel with this architectural paradigm shift, new Very Deep Submicron (VDSM) silicon processes have more and more impact on the performances and deeply modify the way a VLSI system is designed even at the first stages of a design flow. In such a context where many new technological and system related variables enter the game, early exploration of the impact of design choices becomes crucial to estimate the performance of the system to design and reduce its time-to-market. In this context, this thesis presents: - A study of state-of-the-art tools and methods used to estimate the performances of VLSI systems and an original classification based on several features and concepts that they use. Based on this comparison, we highlight their weaknesses and lacks to identify new opportunities in performance prediction. - The definition of new concepts to enable the automatic exploration of large design spaces based on flexible performance criteria and degrees of freedom representing design choices. - The implementation of a couple of two new tools of our own: - Nessie, a tool enabling hierarchical representation of an application along with its platform and automatically performs the mapping and the estimation of their performance. -Yeti, a C++ library enabling the defintion and value estimation of closed-formed expressions and table-based relations. It provides the user with input and model sensitivity analysis capability, simulation scripting, run-time building and automatic plotting of the results. Additionally, Yeti can work in standalone mode to provide the user with an independent framework for model estimation and analysis. To demonstrate the use and interest of these tools, we provide in this thesis several case studies whose results are discussed and compared with the literature. Using Yeti, we successfully reproduced the results of a model estimating multi-core computation power and extended them thanks to the representation flexibility of our tool. We also built several models from the ground up to help the dimensioning of interconnect links and clock frequency optimization. Thanks to Nessie, we were able to reproduce the NoC power consumption results of an H.264/AVC decoding application running on a multicore platform. These results were then extended to the case of a 3D die stacked architecture and the performance benets are then discussed. We end up by highlighting the advantages of our technique and discuss future opportunities for performance prediction tools to explore.

The work presented in this thesis aims at validating an original multicriteria performances estimation tool, NESSIE, dedicated to the prediction of performances to accelerate the design of electronic embedded systems. This tool has been developed in a previous thesis to cope with the limitations of existing design tools and offers a new solution to face the growing complexity of the current applications and electronic platforms and the multiple constraints they are subjected to. More precisely, the goal of the tool is to propose a flexible framework targeting embedded systems in a generic way and enable a fast exploration of the design space based on the estimation of user-defined criteria and a joint hierarchical representation of the application and the platform. In this context, the purpose of the thesis is to put the original framework NESSIE to the test to analyze if it is indeed useful and able to solve current design problems. Hence, the dissertation presents : - A study of the State-of-the-Art related to the existing design tools. I propose a classification of these tools and compare them based on typical criteria. This substantial survey completes the State-of-the-Art done in the previous work. This study shows that the NESSIE framework offers solutions to the limitations of these tools. - The framework of our original mapping tool and its calculation engine. Through this presentation, I highlight the main ingredients of the tool and explain the implemented methodology. - Two external case studies that have been chosen to validate NESSIE and that are the core of the thesis. These case studies propose two different design problems (a reconfigurable processor, ADRES, applied to a matrix multiplication kernel and a 3D stacking MPSoC problem applied to a video decoder) and show the ability of our tool to target different applications and platforms. The validation is performed based on the comparison of a multi-criteria estimation of the performances for a significant amount of solutions, between NESSIE and the external design flow. In particular, I discuss the prediction capability of NESSIE and the accuracy of the estimation. -The study is completed, for each case study, by a quantification of the modeling time and the design time in both flows, in order to analyze the gain achieved by our tool used upstream from the classical tool chain compared to the existing design flow alone. The results showed that NESSIE is able to predict with a high degree of accuracy the solutions that are the best candidates for the design in the lower design flows. Moreover, in both case studies, modeled respectively at a low and higher abstraction level, I obtained a significant gain in the design time. However, I also identified limitations that impact the modeling time and could prevent an efficient use of the tool for more complex problems. To cope with these issues, I end up by proposing several improvements of the framework and give perspectives to further develop the tool.

Driven by the increasing capacity of integrated circuits, multiprocessorsystems-on-chip (MPSoCs) are widely used in modern consumer electron-ics devices. In this thesis, the performance analysis and implementationmethodologies are explored to design predictable streaming applications onMPSoCs computing platforms. The application functionality and concur-rency are described in synchronous data flow (SDF) computational models,and two state-of-the-art architecture templates are adopted as multiproces-sor architectures, i.e., network-on-chip (NoC) based MPSoC and hybrid re-configurable CPU/FPGA platforms. Based on the author’s contributions onsimulation and formal analytical methods, performance analysis and designspace exploration for embedded MPSoCs architectures have been addressed. An energy efficient design space exploration flow is proposed for stream-ing applications with guaranteed throughput on NoC based MPSoCs, in whichboth application throughput analysis and system energy calculation are car-ried out by simulation on a multi-clocked synchronous modelling frame-work. On the other hand, based on event models of data streams, a formalanalytical scheduling framework for real-time streaming applications withminimal buffer requirement on hybrid CPU/FPGA architectures is exploited.The scheduling problem has been formalized declaratively by constraint basetechniques, and solved by a public domain constraint solver. Consecutively,the constraint based method has been extended to solve problems rangingfrom global computation/communication scheduling and reconfiguration anal-ysis to Pareto efficient design. Finally, a prototype of stream processing sys-tem on FPGA based MPSoC is built to substantiate the results from theoreti-cal studies in this thesis. / QC 20101207 / SysModel / Andres