Ce mémoire traite des systèmes intégrés sur puce (System-on-Chip) à faible consommation d'énergie tels que ceux qui seront utilisés dans les équipements portables de future génération (ordinateurs de poche (PDA), téléphones mobiles). S'agissant d'équipements alimentés par des batteries, la consommation énergétique est un problème critique. <p><p>Ces plateformes contiendront probablement une douzaine de coeurs de processeur et une quantité importante de mémoire embarquée. Une architecture de communication optimisée sera donc nécessaire afin de les interconnecter de manière efficace. De nombreuses architectures de communication ont été proposées dans la littérature: bus partagés, bus pontés, bus segmentés et plus récemment, les réseaux intégrés (NoC).<p><p>Toutefois, à l'exception des bus, la consommation d'énergie des réseaux d'interconnexion intégrés a été largement ignorée pendant longtemps. Ce n'est que très récemment que les premières études sont apparues dans ce domaine.<p><p>Cette thèse présente:<p><p>- Une analyse complète de l'espace de conception des architectures de communication intégrées. Sur base de cet espace de conception et d'un état de l'art détaillé, des techniques jusqu'alors inexplorées ont pu être identifiées et investiguées. <p>- La conception d'environnements de simulation de bas et haut niveaux permettant de réaliser des comparaisons entre différentes architectures de communication en termes de consommation énergétique et de surface.<p>- La conception et la validation d'une architecture de communication intégrée innovante basée sur le multiplexage spatial<p><p>Ce dernier point a pour ambition de démontrer qu'un réseau basé sur le multiplexage spatial (SDM) constitue une alternative intéressante aux réseaux classiques principalement basés sur le multiplexage temporel dans le contexte très spécifique des architectures de communication intégrées.<p><p>Nous démontrerons la validité de la solution proposée à l'aide de campagnes de simulation de haut niveau pour divers types de trafic ainsi que des simulations de plus bas niveau. L'étude concerne successivement la conception de routers SDM, des interfaces réseau et finalement d'un réseau complet. Les avantages et inconvénients d'une telle technique seront discutés en détails. / Doctorat en sciences appliquées / info:eu-repo/semantics/nonPublished

Dieser Vortrag stellt einen neuartigen Prüfstand vor, mit welchem das Chip & Cut Verhalten von Elastomeren charakterisiert werden kann. Sowohl theoretischer Hintergrund als auch praktische Erkenntnisse werden diskutiert. Die Vorstellung der Praxisrelevanz dieser Untersuchungen steht im Fokus des Vortrags.

During the past years has the Nostrum Network on Chip (NoC) been developed to become a competitive platform for network based on-chip communication. The Nostrum NoC provides a versatile communication platform to connect a large number of intellectual properties (IP) on a single chip. The communication is based on a packet switched network which aims for a small physical footprint while still providing a low communication overhead. To reduce the communication network size, a queue-less network has been the research focus. This network uses de ective hot-potato routing which is implemented to perform routing decisions in a single clock cycle. Using a platform like this results in increased design reusability, validated signal integrity, and well developed test strategies, in contrast to a fully customised designs which can have a more optimal communication structure but has a significantly longer development cycle to verify the new design accordingly. Several factors are considered when designing a communication platform. The goal is to create a platform which provides low communication latency, high throughput, low power consumption, small footprint, and low design, verification, and test overhead. Proximity Congestion Awareness is one technique that serves to reduce the network load. This leads to that the latency is reduced which also increases the network throughput. Another technique is to implement low latency paths called Data Motorways achieved through a clocking method called Globally Pseudochronous Locally Synchronous clocking. Furthermore, virtual circuits can be used to provide guarantees on latency and throughput. Such guarantees are dificult in hot-potato networks since network access has to be ensured. A technique that implements virtual circuits use looped containers that are circulating on a predefined circuit. Several overlapping virtual circuits are possible by allocating the virtual circuits in different Temporally Disjoint Networks. This thesis summarise the impact the presented techniques and methods have on the characteristics on the Nostrum model. It is possible to reduce the network load by a factor of 20 which reduces the communication latency. This is done by distributing load information between the Switches in the network. Data Motorways can reduce the communication latency with up to 50% in heavily loaded networks. Such latency reduction results in freed buffer space in the Switch registers which allows the traffic rate to be increased with about 30%. / QC 20101122

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Hybrid pixel detectors are widely used in many fields, including military, environment, industry and medical treatment. When integrating such a detector, a vertical connection technique called flip-chip bonding is almost the only way to realize the high-density interconnection between each pixel detector to the read-out chip. Such bonding can offer high-density I/O and a short interconnect distance, which can make the resulting device show excellent performance. Electro deposition is a promising approach to enable a low cost and high yield bump bonding process, compared with conventional sputtering or evaporation which is currently utilized for small-scale production. Due to that, Indium bumping process using electroplating is selected, as a result of which indium bump arrays with a pitch of 220 μm and a diameter of 30 μm have been fabricated using a standard silicon wafer processing. UBM (under bump metallization) for indium bumping was Ti/Ni (300 Å/ 2000 Å). It helps to increase adhesion between the wafer and the bumps and also serves as an excellent diffusion barrier both at room temperature and at 200°C. The indium is electroplated, using an indium sulfamate plating bath, and then formed into bumps through a reflow process. The reflow is made on a 200°C hot plate with a continuous flow of nitrogen over the wafer. During the reflow the indium is melted and forms into bumps due to surface tension. All the corresponding procedural processing steps and results are incorporated in this paper.

The objective of the proposed research is to design, fabricate, characterize and test silicon-embedded magnetic components for on-chip integrated power applications. Driven by the trend towards continued system multi-functionality and miniaturization, MEMS technology can be used to enable fabrication of three-dimensional (3-D) functional devices into the silicon bulk, taking advantage of the 'dead volume' in the substrate and achieving a greater level of miniaturization and integration. As an example, one of the challenges in realizing ultra-compact high-frequency power converters lies in the integration of magnetic components due to their relatively large volume. Embedding 3-D magnetic components within the wafer volume and implementing high-power, through-wafer interconnect for connection to circuitry on the wafer surface is a promising solution for achieving ultra-compact power converters, in which digital control circuitry and power switches are located on the wafer surface, and suitable magnetic components are embedded within the silicon substrate. In order to do this, key tasks in the following areas have been accomplished: development of new fabrication technologies for silicon embedding and 3-D structure realization; creation of high-current, through-wafer interconnects for connection of the device to circuitry; ability to incorporate a variety of magnetic materials when performance enhancement of the device is needed; exploration of a new design space for the devices due to ultra-compactness and silicon interaction; understanding of the complicated loss mechanisms in the embedded devices; and demonstration of device performance and in-circuit operation.

International Telemetering Conference Proceedings / October 21, 2002 / Town & Country Hotel and Conference Center, San Diego, California / FPGAs are increasingly being employed for building real-time signal processing systems. They have been used extensively for implementing the PHY in software radio architectures. This paper provides a technology and market perspective on the use FPGAs for signal processing and demonstrates FPGA DSP using an adaptive channel equalizer case study.

Circadian clocks are biochemical mechanisms that allow eukaryotic and some prokaryotic organisms to coordinate their physiology with daily environmental changes. It enables organisms to increase their fitness by taking advantage of beneficial environmental conditions while also avoiding or restricting certain sensitive processes during harsh conditions. Similarly, post-translational histone modifications allow eukaryotic organisms to regulate gene expression in response to environmental or developmental factors. Some post-translational modifications of histones are associated with active transcription while others are associated with repressed transcription depending upon the location, type and degree of modification. Trimethylation of lysine 4 on the N-terminal tail of histone H3 (H3K4me3) near a gene's promoter has been linked to active transcription of that gene in several organisms. The purpose of the current study was to investigate whether the amount of H3K4me3 at promoters of three specific genes shows a circadian rhythm in Chlamydomonas reinhardtii, a unicellular green alga. Two of the genes had previously been shown to display a circadian rhythm of expression with opposite phase (LHCBM6 and JMJD6-like2), while the third gene is constitutively expressed (RACK1). Quantitative PCR was used to determine the amount of immunoprecipitated H3K4me3 over a circadian cycle. It was hypothesized that H3K4me3 amount at the JMJD6-like2 and LHCBM6 promoter would show a circadian rhythm with a phase correlating directly with the phase of each gene’s rhythm of expression. Conversely, the H3K4me3 amount at the RACK1 promoter was predicted to not show a circadian rhythm, as the gene is constitutively expressed. Instead, results showed that H3K4me3 amount exhibits a circadian rhythm with identical phase for all three genes. ANOVA confirmed that the rhythms were not significantly different between the three genes. General histone H3 amount at promoters did not show a circadian rhythm across any of the three genes. Since recent genome-wide studies in mouse liver revealed a circadian rhythm of H3K4me3 amount with identical phase at the promoter of many genes with diverse expression, the findings presented here suggest that C. reinhardtii might show a similar global regulation of rhythmic H3K4me3 as in mice and that, therefore, this feature has been preserved during eukaryotic evolution.

Plant embryogenesis is an intriguing developmental process that is controlled by many genes. AGAMOUS Like 15 (AGL15) is a MADS-domain transcriptional regulator that accumulates preferentially during this stage. However, at the onset of this work it was unknown which genes are regulated by AGL15 or how AGL15 is regulated. This dissertation is part of the ongoing effort to understand the biological roles of AGL15. To decipher how AGL15 functions during plant development, a chromatin immunoprecipitation (ChIP) approach was adapted to obtain DNA fragments that are directly bound by AGL15 in vivo. Putative AGL15 targets were isolated, and binding and regulation was confirmed for one such target gene, ABF3. In addition, microarray experiments were performed to globally assess genes that are differentially expressed between wild type and agl15 young seeds. Among them, a gene, At5g23405, encoding an HMGB domain protein was identified and its response to AGL15 was confirmed. Preliminary results suggest that the loss-of-function of At5g23405 might have an effect on somatic embryogenesis, consistent with AGL15 repression of the expression of this gene. Lastly, to address the question about how the regulator is regulated, the cis elements controlling the expression of AGL15 must be identified. Deletion analysis of the AGL15 promoter indicated the presence of putative positive and negative cis elements contributing to the expression of AGL15. Further analysis suggested that AGL15 regulates the expression of its own gene and this regulation may partially be explained by the direct binding of the protein to the AGL15 promoter. The data presented in this dissertation demonstrate that ChIP can be used to identify previously unsuspected targets of AGL15. Based on ChIP, a ChIP-chip technique is being developed in the lab to allow a more global analysis of in vivo binding sites. The identification of target genes and cis elements in AGL15 promoter is a step towards characterization of the biological roles of AGL15.