The aim of this project was to produce an integrate-able free space optical transceiver for Specks. Specks are tiny computing units that together can form a powerful network called a SpeckNet. The SpeckNet platform is developed by the SpeckNet consortium, which consists of five Scottish Universities and combines computer science, electrical engineering and digital signal processing groups. The principal goal of creating an optical transceiver was achieved by integrating in-house fabricated VCSELs (with lasing thresholds below 400 uA) and custom designed detectors on the SpeckNet platform. The transceiver has a very low power consumption (approximately 100 uW), which removes the need for synchronous communication through the SpeckNet thus making the network more efficient. I describe both static and dynamic beam control techniques. For static control, I used micro-lenses. I fabricated the lenses by greyscale electron beam lithography and integrated them directly on VCSEL arrays. I achieved a steering angle of 10 degrees with this design. I also looked at integrated gratings etched straight into a VCSEL and observed beam steering with an efficiency of 60% For dynamic control, I implemented a liquid crystal (LC) design. I built a LC cell with 30 individually controlled pixels, but I only achieved a steering angle of 1 degree. Furthermore, I investigated two different techniques for achieving beam steering by interference, using coupled VCSELs (a phased array approach). Firstly, using photonic crystals etched into the surface of the VCSEL, I built coupled laser cavities. Secondly, I designed and built bow-tie type VCSELs that were optically coupled but electrically isolated. These designs work by differential current injection causing an interference effect in the VCSELs far field. This technique is the first stepping stone towards realising a phased optical array. Finally, I considered signal detection. Using the same VCSEL material, I built a resonant-cavity detector. This detector had a better background rejection ratio than commercially available silicon devices.

Les futurs calculateurs de haute performance (HPC) devront faire face à deux défis majeurs : la densité de la bande passante d'interconnexion et les problématiques de consommation d'énergie. La photonique silicium est aujourd’hui perçue comme une solution solide pour aborder ces questions, tant du fait de ses performances que de sa viabilité économique en raison de sa compatibilité directe avec la microélectronique CMOS. Actuellement, une tendance de fond conduit à remplacer les interconnexions métalliques par des liens optiques ; cette évolution a été initiée sur des liaisons grandes distances mais atteint actuellement le niveau des liaisons entre cartes électroniques et pourrait conduire à moyen terme à l’intégration de liens optiques au sein mêmes des circuits intégrés électroniques. La prochaine étape est en effet envisagée pour l'interconnexion des processeurs au sein de puces multi-cœurs en positionnant les liens photoniques sur un même support de silicium (« interposer »). Plusieurs travaux ont démontré la possibilité d'intégrer tous les éléments nécessaires pour la réalisation de liaisons optiques sur un substrat de silicium ouvrant des perspectives de co-intégration optique et électronique très riches.Dans ce contexte, la première contribution de cette thèse est l'optimisation d'un lien de photonique de silicium en terme d'efficacité énergétique par bit (à minimiser). L'optimisation que nous avons conduite a pris en compte une modélisation de la consommation d'énergie pour le laser de la liaison, celle de l’étape dé-sérialisation des données, du résonateur en anneau considéré comme modulateur optique et des circuits de réception (« front-end ») et de décision. Les résultats ont montré que les principales contributions à la consommation de puissance au sein d’un lien optique sont la puissance consommée par le laser et les circuits d’alimentation du modulateur électro-optique. En considérant des paramètres de consommation extraits de simulations numériques et de travaux publiés dans des publications récentes, le débit optimal identifié se trouve dans la plage comprise entre 8 Gbits/seconde et 22 Gbits/seconde selon le nœud technologique CMOS utilisé (65nm à 28nm FD SOI). Il est également apparu qu’une diminution de la consommation de puissance statique du modulateur utilisé pourrait encore ramener ce débit optimal en-dessous de 8 Gbits/seconde.Afin de vérifier ces résultats, un circuit intégré récepteur de liaison optique a été conçu et fabriqué en se basant sur un débit de fonctionnement de 8 Gbits/seconde. Le récepteur utilise une technique d’entrelacement temporel destinée à réduire la vitesse d'horloge nécessaire et à éviter potentiellement l’étape de dé-sérialisation dédiée des informations. / Future high performance computer (HPC) systems will face two major challenges: interconnection bandwidth density and power consumption. Silicon photonic technology has been proposed recently as a cost-effective solution to tackle these issues. Currently, copper interconnections are replaced by optical links at rack and board level in HPCs and data centers. The next step is the interconnection of multi-core processors, which are placed in the same package on silicon interposers, and define the basic building blocks of these computers. Several works have demonstrated the possibility of integrating all elements needed for the realization of short optical links on a silicon substrate.The first contribution of this thesis is the optimization of a silicon photonic link for highest energy efficiency in terms of energy per bit. The optimization provides energy consumption models for the laser, a de- and serialization stage, a ring resonator as modulator and supporting circuitry, a receiver front-end and a decision stage. The optimization shows that the main consumers in optical links is the power consumed by the laser and the modulator's supporting circuitry. Using consumption parameters either gathered by design and simulation or found in recent publications, the optimal bit rate is found in the range between 8 Gbps and 22 Gbps, depending on the used CMOS technology. Nevertheless, if the static power consumption of modulators is reduced it could decrease even below 8 Gbps.To apply the results from the optimization an optical link receiver was designed and fabricated. It is designed to run at a bit rate of 8 Gbps. The receiver uses time interleaving to reduce the needed clock speed and aleviate the need of a dedicated deserialization stage. The front-end was adapted for a wide dynamic input range. In order to take advantage of it, a fast mechanism is proposed to find the optimal threshold voltage to distinguish ones from zeros.Furthermore, optical clock channels are explored. Using silicon photonics a clock can be distributed to several processors with very low skew. This opens the possibility to clock all chips synchronously, relaxing the requirements for buffers that are needed within the communication channels. The thesis contributes to this research direction by presenting two novel optical clock receivers. Clock distribution inside chips is a major power consumer, with small adaptation the clock receivers could also be used inside on-chip clocking trees.

This PhD thesis is devoted to study electro-optic properties of Gemanium/Silicon-Germanium (Ge/SiGe) multiple quantum wells (MQWs) for light modulation, detection, and emission on Si platform. It reports the first development of high speed, low energy Ge/SiGe electro-absorption modulator in a waveguide configuration based on the quantum-confined Stark effect (QCSE), demonstrates the first Ge/SiGe photodiode with high speed performance compatible with 40 Gb/s data transmission, and realizes the first Ge/SiGe light emitting diode based on Ge direct gap transition at room temperature. Extensive DC and RF measurements were performed on each tested prototype, which was realized using the same epitaxial growth and fabrication process. Simple theoretical models were employed to describe experimental properties of the Ge/SiGe MQWs. The studies show that Ge/SiGe MQWs could potentially be employed as a new photonics platform for the development of a high speed optical link fully compatible with silicon technology.

To accommodate the growing demand on higher speeds, low latencies and low energy consumption, the interconnections within and between data centers are supposed to be implemented as optical fiber and waveguide interconnects in future. Optical fiber interconnects provide several advantages over their electrical counterparts as they enable higher bandwidth densities and lower losses at high frequencies over distances longer than few centimeters. However, nowadays optical fiber interconnects are usually not very energy-efficient. The systems in optical networks are mostly optimized for running at their peak performance to transmit the information with the highest available error-free data rate. But the work load of a processor system and hence of an optical link is not constant and varies over time due to the demand of the running applications and users. Therefore, optical interconnects consume the same high power at all times even if lower performance is required. In this paper a new method for the tuning of optical interconnects for on-board and board-to-board optical communication is described. In this way the performance of the transceiver systems of the link is adapted to the present transmission workload and link requirements. If for example lower data rates are required, the bandwidth and therefore the power consumption of the systems can be reduced. This tuning is enabled by the integrated circuitry of the optical link. Different methods for such an adaptive tuning are described and several practical examples are reviewed. By using adaptive bandwidth reduction in the circuits, more than 50 % of the consumed power can be saved. These savings can result in tremendous reductions of the carbon footprint and of the operating costs produced by data centers.

No description available.

Cette thèse est consacrée à l’étude des propriétés optiques et optoélectroniques autour de la bande interdite directe des structures à puits quantiques Ge/SiGe pour la modulation, la photodétection et l’émission de lumière sur la plateforme silicium. Les principaux composants réalisés sont : un modulateur optique en guide d’onde, rapide et à faible puissance électrique, basé sur l’Effet Stark Confiné Quantiquement, les premières photodiodes Ge/SiGe dont le comportement fréquentiel est compatible avec les transmissions de données à 40 Gbit/s, et la première diode à électroluminescence à puits quantiques Ge/SiGe, base sur la transition directe de ces structures et fonctionnant à température ambiante. Les caractérisations statiques et fréquentielles ont été réalisées sur l’ensemble des composants, qui ont tous été fabriqués avec la même structure épitaxiée et les mêmes procédés de fabrication. Des modèles théoriques simples ont ensuite été utilisés pour décrire analyser les comportements observés. Finalement les études menées permettent de conclure que les structures à puits quantiques Ge/SiGe sont un candidat de choix pour la réalisation d’une nouvelle plateforme photonique à haut débit, totalement compatible avec les technologies silicium. / This PhD thesis is devoted to study electro-optic properties of Gemanium/Silicon-Germanium (Ge/SiGe) multiple quantum wells (MQWs) for light modulation, detection, and emission on Si platform. It reports the first development of high speed, low energy Ge/SiGe electro-absorption modulator in a waveguide configuration based on the quantum-confined Stark effect (QCSE), demonstrates the first Ge/SiGe photodiode with high speed performance compatible with 40 Gb/s data transmission, and realizes the first Ge/SiGe light emitting diode based on Ge direct gap transition at room temperature. Extensive DC and RF measurements were performed on each tested prototype, which was realized using the same epitaxial growth and fabrication process. Simple theoretical models were employed to describe experimental properties of the Ge/SiGe MQWs. The studies show that Ge/SiGe MQWs could potentially be employed as a new photonics platform for the development of a high speed optical link fully compatible with silicon technology.

This paper describes technology and process development for a hybrid lithography approach pairing UV-lithography for planar single mode waveguides with 2-photon-polymerization direct-laser-writing for out-of-plane coupling mirrors. Improvements to multi-layer direct patterning of OrmoCore/-Clad material system using UV-lithography are presented. Near square core cross sections are achieved. Minimum alignment accuracy at ≈ 3 μm is observed. Cut-back measurement on single mode waveguides shows attenuation of 0.64 dB cm −1 and 1.5 dB cm −1 at 1310 nm and 1550 nm respectively. Up to 2.5-times increase of shear-strength after thermal exposure up to 300 ◦ C is found using shear tests and compared for various surface treatments. Mechanical compatibility to reflow soldering is derived. An extensive study on the pattering of ORMOCER® using 2-photon-polymerization is performed. Flat 45 ◦ -micro mirrors with sub-10 μm dimensions are 3D-printed both in OrmoCore and OrmoComp. Outlook to further research on hybrid lithography integration approach is given.

This paper describes design and advances in process development for UV-lithography of planar single mode waveguides with openings for out-of-plane coupling µ-mirrors. Improvements to multi-layer direct patterning of OrmoCore/-Clad material system using UV-lithography are presented. Near square core cross sections are achieved. However, non uniformity across 4” wafer is shown due to varying proximity and UV-intensity. Openings in full stack with steep sidewalls without residual layer are patterned. Reduction in stack thickness for very small exposure doses due to inhibition even under inert atmosphere is shown. 45° -µ-mirrors are integrated in these openings to manufacture a U-link via a single mode waveguide and two adjacent micro-mirrors. Optical characterization of U-link demonstrates the feasibility of hybrid lithography approach. However, non-uniformity of core cross-section leads to cross coupling of planar waveguides. Outlook to further research on UV-lithography of multi-layer waveguide stack and alignment with µ-mirror printing is given.

This paper describes advances in hybrid-lithography process, combining UV-lithography for planar, single mode redistribution layer (RDL) and 2-photon-polymerization direct-laser-writing (2PP-DLW) for micro-mirrors inside RDL-opening. Improvements to multi-layer direct patterning of OrmoCore/-Clad material system using UV-lithography and need for broadband UV-LED source are presented. Near square core cross sections and smooth sidewalls are achieved. Openings in full stack with steep sidewalls without residual layer are patterned. To optimize 2PP-DLW-process processing window for both OrmoComp and IP-DIP is thoroughly characterized. Roughness measurements prove feasibility even of coarsely printed structure as reflective μ-mirror for 1550 nm wavelength. Finally these results are applied to periscope probe for wafer-level-testing of edge emitting lasers and proof of concept is shown. Outlook to further research on UV-lithography of multi-layer waveguide stack and alignment with μ-mirror printing is given.