A single-stage high-power-factor electronic ballast with class E inverter is proposed for driving the fluorescent lamp. The circuit configuration is obtained from the integration of a buck-boost converter for power-factor- correction (PFC) and a class E resonant inverter for ballasting. The integrated ballast circuit requires only one active power switch and simple control. Operating the buck-boost converter in discontinuous conduction mode (DCM) at a fixed frequency, the electronic ballast can achieve nearly unity power factor. With pulse-width-modulation (PWM), the electronic ballast can provide an appropriate filament current for preheating, a high voltage for ignition, and then a desired lamp current for steady-state operation. An additional control circuit is included to eliminate the glow current during preheating stage. The operation of the ballast-lamp circuit is analyzed by fundamental approximation. Computer simulations are made and design equations are derived on basis of the power-dependent resistance model of the fluorescent lamp. With carefully designed circuit parameters, the active power switch can be switched on at zero current to reduce the switching losses leading to a higher efficiency. An experimental circuit designed for a PL-27W compact fluorescent lamp is built and tested to verify the computer simulations and analytical predictions. Experimental results show that satisfactory performances can be obtained on the proposed electronic ballast.

This Master Thesis presents a design methodology to a boost PFC converter operating as an Uninterruptible Power Supply rectifier input stage. This methodology defines, making use of a group of current ripples and switching frequencies, the converter minimum volume point analyzing the volumes of the boost inductor, the electromagnetic interference filter and the heat-sinks. Thus, it's developed along this work, each design mentioned above, analyzing the impact of different magnetic materiaIs, input filter topologies and semiconductors technologies. Previously, it is designed the controller and it is developed a simulation structure. ln a second moment, it's designed the boost inductor for a predetermined temperature elevation. After this, it's designed the electromagnetic filter analyzing the impact of different topologies. The heat-sinks are also designed to guarantee the semiconductors operation within the temperature limits. Finally, the methodology based on the previous designs is accomplished, using the procedures and equations already mentioned, becoming possible to define the converter minimum volume point. / Esta Dissertação de Mestrado apresenta uma metodologia de projeto para o conversor boost operando como estágio retificador de entrada em uma fonte de alimentação ininterrupta. Essa metodologia se baseia em definir, através de um conjunto de freqüências de comutação e ondulações de corrente, o ponto de minimização do volume do conversor considerando o volume do indutor, do filtro de interferência eletromagnética conduzida e dos dissipadores. Assim, é desenvolvido ao longo desse trabalho o projeto de cada elemento mencionado estudando o impacto do uso de diferentes materiais magnéticos, topologias de filtro de entrada e tecnologias de semicondutores. Inicialmente é projetado o controlador e desenvolvida a estrutura de simulação do conversor. Em um segundo momento é projetado o indutor boost para uma determinada elevação de temperatura. A seguir é projetado o filtro de interferência eletromagnética analisando o impacto de diferentes topologias. Também são projetados os dissipadores que garantem a operação dos semicondutores dentro dos limites de temperatura estabelecidos pelos fabricantes. Por fim, é formalizada a metodologia baseada nos projetos anteriores, pela qual, fazendo uso dos procedimentos e equações fornecidos, torna-se possível definir o ponto de minimização do volume do conversor.

This Thesis examines the operation and dynamic performance of a single-stage, single-switch power factor corrector, S4 PFC, with an integrated magnetic device, IM. Also detailed isthe development and analysis of a high power light emitting diode, HP LED, power factorcorrection converter and proposed voltage regulation band control approach.The S4 PFC consists of a cascaded discontinuous current mode, DCM, boost stage anda continuous current mode, CCM, forward converter. The S4 PFC achieves a high powerfactor, low input current harmonics and a regulated voltage output, utilising a singleMOSFET. A steady-state analysis of the S4 PFC with the IM is performed, identifying theoperating boundary conditions for the DCM power factor correction stage and the CCMoutput voltage regulation stage. Integrated magnetic analysis focuses on understanding theperformance, operation and generated flux paths within the IM core, ensuring the device doesnot affect the normal operation of the converter power stage. A design method for the S4 PFCwith IM component is developed along with a cost analysis of this approach. Analysis predictsthe performance of the S4 PFC and the IM, and the theoretical work is validated by MATLABand SABER simulations and measurements of a 180 W prototype converter.It is not only the development of new topological approaches that drives theadvancement of power electronic techniques. The recent emergence of HP LEDs has led to aflurry of new application areas for these devices. A DCM buck-boost converter performs thepower factor correction and energy storage, and a cascaded boundary conduction current modebuck converter regulates the current through the LED arrays. To match the useful operatinglifetime of the HP LEDs, electrolytic capacitors are not used in the PFC converter. Analysisexamines the operation and dynamic characteristics of a PFC converter with low capacitiveenergy storage capacity and its implications on the control method. A modified regulationband control approach is proposed to ensure a high power factor, low input current harmonicsand output voltage regulation of the PFC stage. Small signal analysis describes the dynamicperformance of the PFC converter, Circle Criterion is used to determine the loop stability.Theoretical work is validated by SABER and MATLAB simulations and measurements of a180 W prototype street luminaire.

abstract: As the world becomes more electronic, power electronics designers have continuously designed more efficient converters. However, with the rising number of nonlinear loads (i.e. electronics) attached to the grid, power quality concerns, and emerging legislation, converters that intake alternating current (AC) and output direct current (DC) known as rectifiers are increasingly implementing power factor correction (PFC) by controlling the input current. For a properly designed PFC-stage inductor, the major design goals include exceeding minimum inductance, remaining below the saturation flux density, high power density, and high efficiency. In meeting these goals, loss calculation is critical in evaluating designs. This input current from PFC circuitry leads to a DC bias through the filter inductor that makes accurate core loss estimation exceedingly difficult as most modern loss estimation techniques neglect the effects of a DC bias. This thesis explores prior loss estimation and design methods, investigates finite element analysis (FEA) design tools, and builds a magnetics test bed setup to empirically determine a magnetic core’s loss under any electrical excitation. In the end, the magnetics test bed hardware results are compared and future work needed to improve the test bed is outlined. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2019

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This dissertation presents the derivation, analysis and application issues of advanced topologies with coupled inductors. The proposed innovative solutions can achieve significant performance improvement compared to the state-of-the-art technology. New applications call for high-efficiency high step-up DC-DC converters. The basic topologies suffer from extreme duty ratios and severe rectifier reverse recovery. Utilizing coupled inductor is a simple solution to avoid extreme duty ratios, but the leakage inductance associated with the coupled inductor induces severe voltage stress and loss. An innovative solution is proposed featuring with efficient leakage energy recovery and alleviated rectifier reverse recovery. Impressive efficiency improvement is achieved with a simple topology structure. The coupled inductor switching cell is identified. Topology variations and evaluations are also addressed. The concept that utilizes coupled inductors to alleviate rectifier reverse recovery is then extended, and new topologies suitable for other applications are generated. The proposed concept is demonstrated to solve the severe rectifier reverse recovery that occurs in continuous current mode (CCM) boost converters. Significant profile reduction and power density improvement can be achieved in front-end CCM power factor correction (PFC) boost converters, which are the overwhelmingly choice for use in telecommunications and server applications. This dissertation also proposes topologies to realize the single-stage parallel PFC by utilizing coupled inductors. Compared to the state-of-the-art single-stage PFC converters, the proposed topologies introduce a new power flow pattern that minimizes the bulk-capacitor voltage stress and the switch current stress. / Ph. D.

Around 19% of global power consumption and around 3% of global oil demand is attributable to lighting. After the first incandescent lamp was invented in 1879, more and more energy efficient lighting devices, such as gas discharge lamps, and light-emitting diodes (LED), have been developed during the last century. It is estimated that over 38% of future global lighting energy demand could be avoided by the use of more efficient lamps and ballasts [1]. High intensity discharge (HID) lamps, one category of gas discharge lamp, have been widely used in both commercial and residential lighting applications due to their merits of high efficacy, long life, compact size and good color rendition [2-4]. However, HID lamps require a well-designed ballast to stabilize the negative VI characteristics. A so-called ignitor is also needed to provide high voltage to initiate the gas discharge. Stringent input harmonic current limits, such as the IEC 61000-3-2 Class C standard, are set for lighting applications. It is well-known that high-frequency electronic ballasts can greatly save energy, improve lamp performance, and reduce the ballast size and weight compared with the conventional magnetic ballast. However, a unique phenomenon called acoustic resonance could occur in HID lamps under high-frequency operation. A low-frequency square wave current driving scheme has proved to be the only effective method to avoid acoustic resonance in HID lamps. A typical electronic HID ballast consist of three stages: power factor correction (PFC), DC/DC power regulation and low-frequency DC/AC inverter. The ignitor is usually integrated in the inverter stage. The three-stage structure results in a large size and high cost, which unfortunately offsets the merit of the HID lamp, especially in low-wattage applications. In order to make HID lamps more attractive in low-wattage and indoor applications, it is critical to reduce the size, weight and cost of HID ballasts. This dissertation is aimed at developing a compact HID with an ultra-compact ballast installed inside the lamp fixture. It is a similar concept to the compact fluorescent lamp (CFL), but it is much more challenging than the CFL. Two steps are explored to achieve high power density of the HID ballast. The first step is to improve the system structure and circuit topology. Instead of a three-stage structure, a two-stage structure is proposed, which consists of a single-stage power factor correction (SSPFC) AC/DC front-end and an unregulated DC/AC inverter/ignitor stage. An SSPFC AC/DC converter is proposed as the front-end. A DCM non-isolated flyback PFC semi-stage and a DCM buck-boost DC/DC semi-stage share the semiconductor switch, driver and PWM controller, so that the component count and cost can be reduced. The proposed SSPFC AC/DC front-end converter can achieve a high power factor, low THD, low bulk capacitor voltage, and the desired power regulation with a simple control circuit. Because the number of high-frequency switches is reduced compared to that of state-of-the-art two-stage HID ballast topologies, the switching frequency can be increased without sacrificing high efficiency, so the passive component size can be reduced. The power density of the whole ballast is increased using this two-stage structure. It results in a 2.5 times power density (6 W/in3) improvement compared to the commercial product (2.4 W/in3). The power density of the converter in discrete fashion usually suffers as a result of poor three-dimensional (3D) volume utilization due to a large component count and the different form factor of different components. In the second step, integration and packaging technologies are explored to further increase the power density. A 3D passive integrated HID ballast is proposed in this dissertation. All power passive components are designed in planar shape with a uniform form factor to fully utilize the three-dimensional space. In addition, electromagnetic integration technologies are applied to achieve structural, functional and processing integration to reduce component volume and labor cost. System partitioning, integration and packaging strategies, and implementation of major power passive integration, including an integrated EMI filter, and an integrated ignitor, will be discussed in the dissertation. The proposed integrated ballast is projected to double the power density of the discrete implementation. By installing the HID ballast inside the lamp fixture, the ambient temperature for the ballast will be much higher than the conventional separately installed ballast, and combined with a reduced size, the thermal condition for the integrated ballast will be much more severe. A thermal simulation model of the integrated ballast is built in the IDEAS simulation tool, and appropriate thermal management methods are investigated using the IDEAS simulation model. Experimental verification of various thermal management methods is provided. Based on the thermal management study, a new integrated ballast with improved thermal design is proposed. / Ph. D.

With the rapid evolving IT technologies, today, the power factor correction (PFC) design is facing many challenges, such as power scalability, high entire-load-range efficiency, and high power density. Power scalability is a very desirable and cost-effective approach in the PFC design in order to keep up with servers' growing power requirements. Higher power density can eventually reduce the converter cost and allows for accommodating more equipment in the existing infrastructures. Driven strongly by economic and environmental concerns, high entire-load-range efficiency is more and more required by various organizations and programs, such as the U.S. Energy Star, Climate Savers, and German Blue Angel. Today, the existing boost PFC is reaching its limitations to meet these challenges simultaneously. Using the cutting-edge semiconductor devices, further efficiency improvement at light load is still needed. There are limited approaches available for increasing the power density due to the large EMI filter and inductor size. Interleaved multi-channel boost PFC is a promising candidate to meet those challenges, but the interleaved boost converter is a less explored area. On the other hand, the multi-channel interleaved buck converter for the VR application has been intensively studied and thoroughly explored. One basic approach of this study is trying to extend the existing knowledge and techniques obtained from multiphase buck converters to the multi-channel interleaved boost converters since there are similarities existed between the multi-phase buck and the multi-channel boost converters. The existing studies about the interleaving impact on the EMI filter design are based on the time domain ripple cancellation effect. This approach is good enough for most of the filter designs. However, unlike the conventional filter designs, the EMI filter design is a specification related process. Both the EMI standard and the EMI measurement are based on the frequency domain spectrum. Limited by the existing analysis approaches, it is difficult to provide a clear picture about how exactly the multi-channel interleaving will impact the EMI filter design. The interleaving impact on the Common Mode (CM) noise also has not been studied in any existing literatures for the same reason. In this study, the frequency domain analysis method was adopted. With the double Fourier integral transformation, a closed-form expression of all the harmonics of the noise sources can be obtained. With all the detailed phase relationship of the switching frequency harmonics and all the side band harmonics, the multi-channel interleaving impact on both the differential mode (DM) and CM filter design can be clearly understood and summarized. According to the design curves provided, the EMI filter size can be effectively reduced by properly choosing the interleaving channel number and the switching frequency. The multi-channel interleaving impact on the output capacitor current ripple is also studied and summarized in this dissertation. It should be pointed out that interleaving only reduces the total input and output current ripples; the inductor current in each channel still has large ripple if small inductance is used. Similar to the multi-phase buck converter, coupling inductors result in different equivalent inductances for input current ripple and inductor current ripple for boost converters. Keeping the inductor current ripple magnitude the same, inverse coupling inductors between the interleaved channels can reduce the inductor size. However, the DM filter size is increased due to larger input current. Based on the investigation on the total magnetic component weight, inverse coupling inductor can reduce the total magnetic component weight. The reduction is more pronounced for lower switching frequency design when the inductor size is dominating among the total magnetic components. Based on the harmonic cancellation, and with all the detailed phase relationship of the switching frequency harmonics and all the side band harmonics, a novel phase angle control method is proposed to maximize the reduction of the EMI filter. For example, in a 2-channel interleaved PFC, just by changing the interleaving scheme to 90 degree phase shift, 39% total volume reduction of the EMI filter can be achieved. The proposed phase angle controlled multi-channel PFC is experimentally demonstrated and verified on a digital controlled 4-channel PFC. The phase angle control method proposed in the multi-channel boost converter can be applied back to the multi-phase buck converter as well. The harmonic cancellation principle will be the same as the multi-channel boost converter. The same benefits can be obtained when the requirement is defined in the frequency domain, e.g. the EMI Standard. The interleaved multi-channel configuration makes it possible to implement the phase-shedding to improve the PFC light load efficiency. By decreasing the number of active channels according to the load, the PFC light load efficiency can be optimized. However, shedding phases can reduce the ripple cancellation effect as well, which will result in the EMI noise increase and losing the benefit on the EMI filter. By applying the proposed phase-shedding with phase angle control strategy, the phase shedding impact on the EMI filter design can be minimized. The light load efficiency can be improved without compromising the EMI filter size. Then, adaptive frequency controlled PFC is proposed to further improve the PFC light load efficiency. The proposed light load efficiency improvement strategies are combined and implemented on the platform of the digital controlled 4-channel PFC. The benefit of improving the light load efficiency is experimentally verified. The EMI performance is also evaluated with the EMI measurement results obtained from the PFC prototype. Following the same approach explored, the benefits of interleaved boost converter can be further extended other applications, such as the boost converter in the Hybrid Electric Vehicles (HEV) and photovoltaic (PV) system. / Ph. D.

The boost power factor correction (PFC) circuit is a common circuit in power electronics. Through years of experience, many designers have optimized the design of these circuits for particular applications. In this study, a new design procedure is presented that guarantees optimal results for any application. The algorithm used incorporates the principles of evolution in order to find the best design. This new design technique requires a rethinking of the traditional design process. Electrical models have been developed specifically for use with the optimization tool. One of the main focuses of this work is the implementation and verification of computationally efficient thermal and electro-magnetic interference (EMI) models for the boost PFC circuit. The EMI model presented can accurately predict noise levels into the 100's of kilohertz range. The thermal models presented provide very fast predictions and they have been adjusted to account for different thermal flows within the layout. This tuning procedure results in thermal predictions within 10% of actual measurement data. In order to further reduce the amount of analysis that the optimization tool must perform, some of the converter design has been performed using traditional methods. This part of the design is discussed in detail. Additionally, a per unit analysis of EMI and thermal levels is introduced. This new analysis method allows EMI and thermal levels to be compared on the same scale thus highlighting the tradeoffs between the both behaviors. / Master of Science

This thesis focuses on the study, implementation and improvement of a digital controller for a power factor correction (PFC) converter. The development of the telecommunications industry and the Internet demands reliable, cost-effective and intelligent power. Nowadays, the telecommunication power systems have output current of up to several kilo amperes, consisting of tens of modules. The high-end server system, which holds over 100 CPUs, consumes tens of kilowatts of power. For mission-critical applications, communication between modules and system controllers is critical for reliability. Information about temperature, current, and the total harmonic distortion (THD) of each module will enable the availability of functions such as dynamic temperature control, fault diagnosis and removal, and adaptive control, and will enhance functions such as current sharing and fault protection. The dominance of analog control at the modular level limits system-module communications. Digital control is well recognized for its communication ability. Digital control will provide the solution to system-module communication for the DC power supply. The PFC converter is an important stage for the distributed power system (DPS). Its controller is among the most complex with its three-loop structure and multiplier/divider. This thesis studies the design method, implementation and cost effectiveness of digital control for both a PFC converter and for an advanced PFC converter. Also discussed is the influence of digital delay on PFC performance. A cost-effective solution that achieves good performance is provided. The effectiveness of the solution is verified by simulation. The three level PFC with range switch is well recognized for its high efficiency. The range switch changes the circuit topology according to the input voltage level. Research literature has discussed the optimal control for both range-switch-off and range-switch-on topologies. Realizing optimal analog control requires a complex structure. Until now optimal control for the three-level PFC with analog control has not been achieved. Another disadvantage of the three-level PFC is the output capacitor voltage imbalance. This thesis proposes an active balancing solution to solve this problem. / Master of Science