Embedded memories dominate area, power and cost of modern very large scale integrated circuits system on chips ( VLSI SoCs). Furthermore, due to process variations, it becomes challenging to design reliable energy efficient systems. Therefore, fault-tolerant designs will be area efficient, cost effective and have low power consumption. The idea of this project is to design embedded memories where reliability is intentionally compromised to increase storage density. Gain cell memories are smaller than SRAM and unlike DRAM they are logic compatible. In multilevel DRAM storage density is increased by storing two bits per cell without reducing feature size. This thesis targets multilevel read and write schemes that provide short access time, small area overhead and are highly reliable. First, timing analysis of reference design is performed for read and write operation. An analytical model of write bit line (WBL) is developed to have an estimate of write delay. Replica technique is designed to generate the delay and track variations of storage array. Design of replica technique is accomplished by designing replica column, read and write control circuits. A memory controller is designed to control the read and write operation in multilevel DRAM. A multilevel DRAM is with storage capacity of eight kilobits is designed in UMC 90 nm technology. Simulations are performed for testing and results are reported for energy and access time. Monte Carlo analysis is done for variation tolerance of replica technique. Finally, multilevel DRAM with replica technique is compared with reference design to check the improvement in access times.

Submitted by PPG Ci?ncia da Computa??o (ppgcc@pucrs.br) on 2018-08-22T17:30:17Z No. of bitstreams: 1 GUILHERME HECK_TES.pdf: 7520580 bytes, checksum: 0abf48b5a455b7c50fa0b30109a1ee57 (MD5) / Approved for entry into archive by Sheila Dias (sheila.dias@pucrs.br) on 2018-08-23T12:09:32Z (GMT) No. of bitstreams: 1 GUILHERME HECK_TES.pdf: 7520580 bytes, checksum: 0abf48b5a455b7c50fa0b30109a1ee57 (MD5) / Made available in DSpace on 2018-08-23T13:31:43Z (GMT). No. of bitstreams: 1 GUILHERME HECK_TES.pdf: 7520580 bytes, checksum: 0abf48b5a455b7c50fa0b30109a1ee57 (MD5) Previous issue date: 2018-03-09 / A demanda sem precedentes por poderosos dispositivos de processamento gerou quebras consecutivas de paradigma de projeto de circuito na ?rea de Circuitos Integrados (CIs). O uso de tecnologia submicrom?trica profunda aumenta a densidade de integra??o a n?veis nunca vistos antes. No entanto, com CIs mais densos, a inclina??o do rel?gio e outros efeitos requerem compensa??es em design s?ncrono, o que pode aumentar a ?rea e o consumo de energia a valores inaceit?veis. Como alternativa, o paradigma ass?ncrono est? re-emergindo, focado na efici?ncia de energia. Entre os modelos cl?ssicos de projeto ass?ncrono, o Empacotamento-de-Dados (ED) se destaca pela sua capacidade de fornecer alto desempenho, reduzir a pot?ncia e obter resultados de ?rea semelhante ? dos modelos s?ncronos. Diferentemente dos modelos mais robustos de quase-atraso insens?vel, uma outra classe comum de modelos para implementar circuitos ass?ncronos, circuitos ED requerem o uso extensivo de Elementos de Atraso (EAs) para garantir a correta funcionalidade. No entanto, todos os circuitos s?o afetados por varia??es de Processo, Tens?o e Temperatura (PTT), incluindo a L?gica Combinacional (LC) em ED impondo margem em elementos de atraso. Al?m disso, projetos atuais usam escalonamento de tens?o para melhorar a efici?ncia de energia, o que afeta o atraso diferentemente em LCs e EAs adicionando mais margem em EAs. Um novo modelo baseado em ED chamado Blade usa o conceito de resili?ncia como uma esperan?a para evitar a margem de atraso causada por PTT e escalonamento de tens?o. Contudo, o uso de dois elementos de atraso ir? representar mais margens e mais tempo de teste no circuito final. Assim, este trabalho mostra uma an?lise do comportamento de elementos de atraso sob escalonamento de tens?o e o impacto em testes p?s-sil?cio. Ele introduz um novo termo para determinar o impacto da escala de tens?o sobre os elementos de atraso e tamb?m a compara??o entre os EAs mais utilizados em projetos ED usando esta nova m?trica. Uma an?lise de testes em modelos ED e Blade ? apresentada e o impacto da escala de tens?o nestes projetos ? analisado. Finalmente, um novo elemento de atraso ? proposto focando na redu??o de margem e redu??o no tempo de teste para o modelo Blade. / The unprecedented demand for powerful processing devices has generated consecutive circuit design paradigm breaks in the Integrated Circuits (ICs) arena. The use of deep submicron technology increases the integration density to levels never seen before. However, with denser ICs, clock skew and other effects require compensations in synchronous design, which can increase area overhead and power consumption to unacceptable values. As an alternative, the asynchronous paradigm is re-emerging, focused on power efficiency. Among classical asynchronous design templates, the Bundled-Data (BD) one stands off for its capability to provide high performance, reduce power and achieve area results similar to that of synchronous designs. Unlike the more robust Quasi-Delay Insensitive (QDI) templates, another common class of templates to implement asynchronous circuits, BD circuits require the extensive use of Delay Elements (DEs) to guarantee correct functionality. However, all circuits are affected by Process, Voltage and Temperature (PVT) variations, including the Combinational Logic (CL) on BD imposing margin on delay elements. In addition, current designs use voltage scaling to improve power efficiency, which impacts the delay differently in CLs and DEs adding more margin in DEs. A new template based on BD called Blade uses resiliency concept as a hope to avoid the delay margin caused by PVT and voltage scaling. Although, the use of two delay elements will represents more margins and extra test time on final circuit. So, this work shows an analysis of delay elements behavior under voltage scaling and the impact on post-silicon tests. It introduces a new term to determine the voltage scaling impact on delay elements and also the comparison between the most used DEs on BD designs using this novel metric. An analysis of tests in BD and Blade templates are presented and the impact of voltage scaling in these designs is analyzed. Finally, a novel delay element is proposed focusing in margin reduction and reduction in test time for Blade template.