Computer graphics is a field whose time has come. In the past, it was an esoteric specialty involving expensive display hardware and idiosyncratic software. Recently, hardware has become more readily available, and efforts have been made to develop graphics software standards, which help make graphics programming rational and straightforward. The Graphical Kernel System (GKS) is rapidly gaining acceptance as a worldwide standard for computer graphics. The International Standards Organization (ISO) is in the final stages of converting GKS from its current status as a Draft International Standard (DIS) to an International Standard. This report presents an overview of GKS and also discusses a subroutine library, that has been developed for use at McMaster University and is equivalent to ”0a" GKS (the lowest level of GKS). This library, called GKSLIB, is written in FORTRAN 77, and could be used by a programmer to support a wide range of two-dimensional, passive graphics applications. / Thesis / Master of Science (MS)

Advanced power semiconductor devices have consistently proven to be a major force in pushing the progressive development of power conversion technology. The emerging wide-band-gap (WBG) material based power semiconductor devices are considered as gaming changing devices which can exceed the limit of silicon (Si) and be used to pursue groundbreaking high-frequency, high-efficiency, and high-power-density power conversion. The switching performance of cascode GaN HEMT is studied at first. An accurate behavior-level simulation model is developed with comprehensive consideration of the impacts of parasitics. Then based on the simulation model, detailed loss breakdown and loss mechanism analysis are studied. The cascode GaN HEMT has high turn-on loss due to the reverse recovery charge and junction capacitor charge, and the common source inductance (CSI) of the package; while the turn-off loss is extremely small attributing to unique current source turn off mechanism of the cascode structure. With this unique feature, the critical conduction mode (CRM) soft switching technique is applied to reduce the dominant turn on loss and significantly increase converter efficiency. The switching frequency is successfully pushed to 5MHz while maintaining high efficiency and good thermal performance. Traditional packaging method is becoming a bottle neck to fully utilize the advantages of GaN HEMT. So an investigation of the package influence on the cascode GaN HEMT is also conducted. Several critical parasitic inductance are identified, which cause high turn on loss and high parasitic ringing that may lead to device failure. To solve the issue, the stack-die package is proposed to eliminate all critical parasitic inductance, and as a result, reducing turn on loss by half and avoiding potential failure mode of the cascode GaN device effectively. Utilizing soft switching and enhanced packaging, a GaN-based MHz totem-pole PFC rectifier is demonstrated with 99% peak efficiency and 700 W/in3 power density. The switching frequency of the PFC is more than ten times higher than the state-of-the-art industry product while it achieves best possible efficiency and power density. Integrated power module and integrated PCB winding coupled inductor are all studied and applied in this PFC. Furthermore, the technology of soft switching totem-pole PFC is extended to a bidirectional rectifier/inverter design. By using SiC MOSFETs, both operating voltage and power are dramatically increased so that it is successfully applied into a bidirectional on-board charger (OBC) which achieves significantly improved efficiency and power density comparing to the best of industrial practice. In addition, a novel 2-stage system architecture and control strategy are proposed and demonstrated in the OBC system. As a continued extension, the critical mode based soft switching rectifier/inverter technology is applied to three-phase AC/DC converter. The inherent drawback of critical mode due to variable frequency operation is overcome by the proposed new modulation method with the idea of frequency synchronization. It is the first time that a critical mode based modulation is demonstrated in the most conventional three phase H-bridge AC/DC converter, and with 99% plus efficiency at above 300 kHz switching frequency. / Ph. D.

Research was undertaken in order to simulate and optimize an Aquatair Model P-3 package sewage treatment plant for which operating data from the National Sanitation Foundation was available. The treatment plant consists essentially of a plastic medium trickling filter mounted overtop of a complete-mix activated sludge (CMAS) tank; the unit also has a primary sludge holding tank and a secondary clarifier. From consideration of reaction kinetics, reactor type, and geometry, a mechanistic model was developed to explain the phenomena of substrate removal in the Aquatair Model P-3. The two-factor SIMPLEX optimization procedure was used to determine the best set of biological reaction constants K1 and K2 which would characterize the substrate removal behavior of the Aquatair biological oxidation tower and recirculation chamber, respectively, based on actual plant data. Once the behavior of the plant was accurately simulated, cost functions were developed in order to relate the various design variables to cost. An n-factor PERPLEX optimization routine was then used to optimize the various plant variables for a given flow, organic load, and efficiency. PERPLEX, a modification of the Box COMPLEX method, was shown to be a useful tool for evaluating the factor space defined by a set of mathematical assumptions. The cost benefit of aerobic digestion occurring in the Aquatair bio-oxidation tower was predicted by the model and confirmed by nitrification data and sludge production calculations. / Master of Science

Previous research shows that software reuse can have a positive impact on software development economics, and that the adoption of a specific open source license can influence how a software product is received by users and programmers. This study attempts to bridge these two research areas by examining how the adoption of an open source license affects software reuse. Two reuse metrics were applied to 9,570 software packages contained in the Fedora Linux software repository. Each package was evaluated to determine how many external components it reuses, as well as how many times it is reused by other software packages. This data was divided into subsets according to license type and software category. The study found that, in general, (1) software released under a restrictive license reuse more external components than software released under a permissive license, and (2) that software released under a permissive license is more likely to be reused than software released under a restrictive license. However, there are exceptions to these conclusions, as the effect of license choice on reuse varies by software category. / Master of Science

The high-voltage SiC power semiconductor devices have been developed in recent years. They cause an urgent in the need for the power semiconductor packaging to have not only low interconnect resistance, less noise, less parasitic oscillations, improved reliability, and better thermal management, but also High-Voltage (HV) blocking capability. The existing power semiconductor packaging technologies includes wire-bonding interconnect, press pack, flip-chip technology, metal posts interconnected parallel plates structure (MIPPS), dimple array interconnection (DAI), power overlay (POL) technology, and embedded power (EP) technology. None of them meets the requirements of low profile and high voltage rating. The objective of the work in this dissertation is to propose and design a high-voltage power semiconductor device packaging method with low electric field stress and low profile to meet the requirments of high-voltage blocking capability. The main contributions of the work presented in this dissertation are: 1. Understanding the electric field distribution in the package. The power semiconductor packaging is simulated by using Finite Element Analysis (FEA) software. The electric field distribution is known and the locations of high electric field concentration are identified. 2. Development of planar high-voltage power semiconductor device packaging method With the proposed structure in the dissertation, the electric field distribution of a planar device package is improved and the high electric field intensity is relieved. 3. Development of design guidelines for the propsed planar high-voltage device packaging method. The influence of the structure dimensions and the material properties is studied. An optimal design is identified. The design guideline is given. 4. Fabrication and experimental verification of the proposed high-voltage device packaging method A detailed fabrication procedure which follows the design guideline is presented. The fabricated modules are tested by using a high power curve tracer. Test results verify the proposed method. 5. Simplification of the structure model of the proposed device package The package structure model is simplified through the elimination of power semiconductor device internal structure model. The simplified model can be simulated by a non-power device simulator. The simulation results of the simplified model match the simulation results of the complete model very well. / Ph. D.

Threshold leak sizes and leak rates were calculated for a number of liquid food products exhibiting a wide range of surface tension and viscosity values. From this data, one can see that mathematically, under typical pressure differentials generated in food packages (less than or equal to ±34.5 kPa), a leak will never start through a 2 μm defect. The calculated leak rates were compared to calculated evaporation rates. The evaporation rate exceeds the leak rate at lower sized microholes (2, and 5 μm diameter) under typical pressure differentials found in food packages. If the liquid, typically aqueous in food products, is evaporating off faster than the leak itself, then there will be solids left behind that could effectively plug the leak. The critical leak size is the size micro-defect that allows microbial penetration into the package. The critical leak size of air-filled defects was found to be 7 μm at all pressures tested. This size is considerably important to food packagers because this is when sterility of the package is lost. Previous leak studies have shown that the critical leak size for liquid-filled defects coincide with the threshold leak size and pressure. If this is in fact true, then air-filled defects should exhibit a larger critical leak size than the liquid-filled defects. In this study, air-filled defects were examined. A bioaerosol exposure chamber was used to test micro-defects, nickel microtubes of known diameters 2, 5, 7, 10, 20, and 50 μm hydraulic diameters, against pressure differentials of 0, -6.9, -13.8, and -34.5 kPa. / Master of Science

Submitted by Maicon Juliano Schmidt (maicons) on 2015-05-21T17:31:45Z No. of bitstreams: 1 Fabiano Alex Colling.pdf: 5692188 bytes, checksum: 8354ca65e4e9e9a92a55f10b5e92b187 (MD5) / Made available in DSpace on 2015-05-21T17:31:45Z (GMT). No. of bitstreams: 1 Fabiano Alex Colling.pdf: 5692188 bytes, checksum: 8354ca65e4e9e9a92a55f10b5e92b187 (MD5) Previous issue date: 2014-11-27 / CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / CNPQ – Conselho Nacional de Desenvolvimento Científico e Tecnológico / FAPERGS - Fundação de Amparo à Pesquisa do Estado do Rio Grande do Sul / FINEP - Financiadora de Estudos e Projetos / NUCMAT - Núcleo de Caracterização de Materiais / Programa de Bolsas de Estudo Talentos Tecnosinos / itt Chip - Instituto Tecnológico de Semicondutores da Unisinos / Hongik University da Coreia do Sul / Modelab - Laboratório de Modelagem Elétrica Térmica e Mecânica de Módulos e Encapsulamentos e Eletrônicos / O desenvolvimento de novas tecnologias de encapsulamento de semicondutores tem diminuído o tamanho das trilhas das placas de circuito impresso em busca da miniaturização. Esta diminuição está chegando ao limite possível de ser construído pelo fato de apresentar problemas, como aumento da resistência, ou por ruptura por eletromigração, além do aumento do custo para o controle de partículas nas salas limpas de fabricação. O Encapsulamento sobre Encapsulamento (Package on Package - PoP) surge como uma proposta de encapsulamento com empilhamento de chips finos para reduzir a ocupação do chip na placa. A diferença de propriedades térmicas e mecânicas dos diferentes materiais que compõem o chip encapsulado pode resultar no empenamento do componente. Neste trabalho, foi simulado o comportamento termomecânico de um dispositivo eletrônico encapsulado pela tecnologia Package on Package. Foi avaliado, do ponto de vista térmico e mecânico, quais são os fatores geradores do empenamento de semicondutores encapsulados com a tecnologia PoP recorrente no processo de moldagem. As condições e parâmetros de processo de fabricação foram estudados durante a fabricação de um protótipo de chip de 40 µm de espessura e moldado com um composto de epóxi do tipo 2 (Epoxy Molding Compound - EMC) realizado no Laboratório de Materiais do Departamento de Ciências dos Materiais e Engenharia da universidade Hongik da Coreia do Sul, parceira no projeto de pesquisa. Através das medições do empenamento, por interferometria de Moiré, realizadas no laboratório de testes da empresa Sul Coreana Hana Micron, foi possível construir correlações com a simulação computacional deste componente. Os resultados desta comparação foram utilizados como base para a validação da simulação e ajustes de dados de entrada utilizados em outras três espessuras diferentes de chip de silício (70, 100 e 200 µm) e dois tipos diferentes de EMC (EMC1 e EMC2). As condições e parâmetros de processo de fabricação, a influência no empenamento das diferentes espessuras e tipos de EMC dos componentes simulados foram avaliados. As simulações realizadas com variação no EMC em componentes com chip de 40 µm mostraram que o EMC do tipo 1 apresenta uma redução de 42,39% no empenamento na parte superior do componente (Top) maior em relação ao EMC do tipo 2. No Top, o substrato com chip de 100 µm, o empenamento foi reduzido em 36,62% e no de 200 µm a redução foi de 3,29%. Os resultados mostram a importância da simulação para prever a tendência do empenamento, quando existe a necessidade de muitas variações de parâmetros de processo de fabricação. / The development of new technologies of semiconductors packaging has reduced the size of the tracks of printed circuit boards in search of miniaturization. This reduction has been reaching its own possible limits (of construction) because it has several problems, such as increase of resistance, rupture by electromigration, in addition to the increase of costs of particles control in manufacturing cleanrooms. Package on Package (PoP) comes as a proposition for encapsulation with thin chips piling in order to reduce chip occupation on the board. The difference in thermal and mechanical properties of the different materials that make up the encapsulated chip may result in the warpage of the component. In this study, the thermomechanical behavior of an electronic device encapsulated by the Package on Package technology was simulated. From the thermal and mechanical point of view, it was evaluated what factors cause the warpage of the semiconductors encapsulated with the PoP technology, warpage which is recurrent in the molding process. The manufacturing process conditions and parameters were assessed/evaluated during the making of a 40μm-thick chip prototype which was molded with a type 2 Epoxi Molding Compound - EMC - in the Materials Laboratory of Hongik University Department of Materials Science and Engineering in South Korea, our partner in this research project. Through the warpage measurements, by Moiré interferometry carried out in South Korean Hana Micron's test laboratory, we managed to build correlations with the computing simulation of this component. The results of this comparison were used as base for validation of the simulation and for adjustment of input data used in three different thickness of silicon chips (70, 100 and 200 μm) and two different EMC (EMC1 and EMC2). The manufacturing process conditions and parameters, the influence in warpage of different thicknesses and simulated components EMC types were evaluated. The simulations carried out with EMC variation in components with 40μm chip demonstrated that type 1 EMC has a decrease in warpage of the upper part of the component (Top) 42.39 percent larger than type 2 EMC. On the Top, the substract plus chip with 100 μm thickness, the warpage was reduced in 36.62 percent, and in the 200 μm chip, the reduction was by 3.29 percent. The results show the importance of simulation to predict warpage tendency, when there is the need for many variations of manufacturing production parameters.

Les travaux présentés dans cette thèse sont une contribution à l'étude d'antennes reconfigurables à base de MEMS en intégration hétérogène 3D pour les systèmes de communication millimétriques. Ces travaux de thèse s'inscrivent dans le cadre d'un projet ANR nommé SIPCOM (Intégration hétérogène 3D (System-In-Package) pour objets communicants en gamme millimétrique), qui concerne l'intégration hétérogène d'un microsystème intelligent communicant à 60GHz. Au cours de ce manuscrit, nous proposons la réalisation d'antennes sur membrane selon 3 technologies. Dans un premier temps, une nouvelle technologie simple et bas coût basée sur un empilement de FR4 et de Pyralux ainsi qu'un nouveau concept d'antenne patch sur membrane alimentée par un guide d'onde intégré via une fente de couplage sont présentés. Dans un second temps, ce nouveau concept d'antenne a été adapté afin de pouvoir l'intégrer au module SiP réalisé en technologie Silicium / BCB. Enfin, la troisième technologie basée sur des substrats de quartz permet de démontrer la faisabilité d'une antenne à balayage électronique pour laquelle chaque excitateur est intégré dans le design d'un déphaseur à base de MEMS permettant de s'affranchir des interconnexions par bonding entre le déphaseur et la partie antennaire. / The work presented in this PhD thesis is a contribution for the study of reconfigurable antennas based on MEMS integration for 3D heterogeneous millimeter communication systems. This study falls within the framework of a ANR project named SIPCOM, for heterogeneous integration of smart millimeter communicating systems. During this manuscript, we propose the implementation of membrane antennas with three technological processes. Firstly, a new simple and low cost technology based on FR4 and Pyralux substrates and a new concept of patch antenna fed by integrated waveguide are investigated. In a second time, this new antenna design has been matched in order to be integrated in the SIP module using Silicon/BCB technology. The third technology based on quartz substrates is used to demonstrate the feasibility of an electronic beamscanning antenna for which one each slot feeder is integrated into the design of the MEMS phase shifter to overcome the bonding interconnections between the phase shifter and the antenna.

Les assemblages PoP pour " Package on Package " permettent d'augmenter fortement la densité d'intégration des circuits et systèmes microélectroniques, par superposition de plusieurs éléments semi-conducteurs actifs. Les interconnexions internes de ces systèmes sont alors soumises à des contraintes jamais atteintes. Nous avons pu identifier, caractériser, modéliser et simuler les mécanismes de défaillance potentiels propres à ces assemblages, et leur évolution : * Les gauchissements dans la phase d'assemblage du " PoP " et ses contraintes thermomécaniques sont plus importants que ceux de chacun des composants individuels. Un modèle analytique original a été construit et mis en ligne afin d'évaluer a priori ce gauchissement. * Les comportements hygroscopiques et hygromécaniques sont simulés et mesurés par une approche originale. L'assemblage " PoP " absorbe plus d'humidité que la somme des deux composants individuels, mais son gauchissement hygromécanique et ses contraintes hygromécaniques sont moins élevées. * Deux types d'essais de vieillissement accéléré sont réalisés pour étudier la fiabilité du " PoP " assemblé sur circuit imprimé : des cycles thermiques et des tests sous fort courant et température élevée. Dans ces deux types d'essais, l'assemblage d'un composant " top " sur un autre composant " bottom " pour former un PoP augmente les risques de défaillances. * L'évolution de la microstructure selon le type de vieillissement est comparée par des analyses physiques et physico-chimiques. Les fissures sont toujours situées dans l'interface substrat/billes, qui correspond aux zones critiques prédites par les simulations.

In realizing a portable chemical analysis system, adequate partitioning of a reusable component and a disposable is required. For successful implementation of micromachined sensors in an instrument, reliable methods for interconnection and interface are in great demand between these two major parts. This thesis work investigates interconnection methods of micromachined chip devices, a hybrid fluidic interface system, and measurement circuitry for completing instrumentation. The interconnection method based on micromachining and injection molding techniques was developed and an interconnecting microfluidic package was designed, fabricated and tested. Alternatively, a plug-in type design for a large amount of sample flow was designed and demonstrated. For the hybrid interface, sequencing of the chemical analysis was examined and accordingly, syringe containers, a peristaltic pump and pinch valves were assembled to compose a reliable meso-scale fluidic control unit. A potentiostat circuit was modeled using a simulation tool. The simulated output showed its usability toward three-electrode electrochemical microsensors. Using separately fabricated microsensors, the final instrument with two different designs--flow-through and plug-in type was tested for chlorine detection in water samples. The chemical concentration of chlorine ions could be determined from linearly dependent current signals from the instrument.