This dissertation presents several cost-effective production test solutions using fault grading and mixed-signal design verification cases enabled by analog behavioral modeling. Although the latest System-on-Chip (SOC) is getting denser, faster, and more complex, the manufacturing technology is dominated by subtle defects that are introduced by small-scale technology. Thus, SOC requires more mature testing strategies. By performing various types of testing, better quality SoC can be manufactured, but test resources are too limited to accommodate all those tests. To create the most efficient production test flow, any redundant or ineffective tests need to be removed or minimized. Chapter 3 proposes new method of test data volume reduction by combining the nonlinear property of feedback shift register (FSR) and dictionary coding. Instead of using the nonlinear FSR for actual hardware implementation, the expanded test set by nonlinear expansion is used as the one-column test sets and provides big reduction ratio for the test data volume. The experimental results show the combined method reduced the total test data volume and increased the fault coverage. Due to the increased number of test patterns, total test time is increased. Chapter 4 addresses a whole process of functional fault grading. Fault grading has always been a ”desire-to-have” flow because it can bring up significant value for cost saving and yield analysis. However, it is very hard to perform the fault grading on the complex large scale SOC. A commercial tool called Z01X is used as a fault grading platform, and whole fault grading process is coordinated and each detailed execution is performed. Simulation- based functional fault grading identifies the quality of the given functional tests against the static faults and transition delay faults. With the structural tests and functional tests, functional fault grading can indicate the way to achieve the same test coverage by spending minimal test time. Compared to the consumed time and resource for fault grading, the contribution to the test time saving might not be acceptable as very promising, but the fault grading data can be reused for yield analysis and test flow optimization. For the final production testing, confident decisions on the functional test selection can be made based on the fault grading results. Chapter 5 addresses the challenges of Package-on-Package (POP) testing. Because POP devices have pins on both the top and the bottom of the package, the increased test pins require more test channels to detect packaging defects. Boundary scan chain testing is used to detect those continuity defects by relying on leakage current from the power supply. This proposed test scheme does not require direct test channels on the top pins. Based on the counting algorithm, minimal numbers of test cycles are generated, and the test achieved full test coverage for any combinations of pin-to-pin shortage defects on the top pins of the POP package. The experimental results show about 10 times increased leakage current from the shorted defect. Also, it can be expanded to multi-site testing with less test channels for high-volume production. Fault grading is applied within different structural test categories in Chapter 6. Stuck-at faults can be considered as TDFs having infinite delay. Hence, the TDF Automatic Test Pattern Generation (ATPG) tests can detect both TDFs and stuck-at faults. By removing the stuck-at faults being detected by the given TDF ATPG tests, the tests that target stuck-at faults can be reduced, and the reduced stuck-at fault set results in fewer stuck-at ATPG patterns. The structural test time is reduced while keeping the same test coverage. This TDF grading is performed with the same ATPG tool used to generate the stuck-at and TDF ATPG tests. To expedite the mixed-signal design verification of complex SoC, analog behavioral modeling methods and strategies are addressed in Chapter 7 and case studies for detailed verification with actual mixed-signal design are ad- dressed in Chapter 8. Analog modeling effort can enhance verification quality for a mixed-signal design with less turnaround time, and it enables compatible integration of the mixed-signal design cores into the SoC. The modeling process may reveal any potential design errors or incorrect testbench setup, and it results in minimizing unnecessary debugging time for quality devices. Two mixed-signal design cases were verified by me using the analog models. A fully hierarchical digital-to-analog converter (DAC) model is implemented and silicon mismatches caused by process variation are modeled and inserted into the DAC model, and the calibration algorithm for the DAC is successfully verified by model-based simulation at the full DAC-level. When the mismatch amount is increased and exceeded the calibration capability of the DAC, the simulation results show the increased calibration error with some outliers. This verification method can identify the saturation range of the DAC and predict the yield of the devices from process variation. A phase-locked loop (PLL) design cases were also verified by me using the analog model. Both open-loop PLL model and closed-loop PLL model cases are presented. Quick bring-up of open-loop PLL model provides low simulation overhead for widely-used PLLs in the SOC and enables early starting of design verification for the upper-level design using the PLL generated clocks. Accurate closed-loop PLL model is implemented for DCO-based PLL design, and the mixed-simulation with analog models and schematic designs enables flexible analog verification. Only focused analog design block is set to the schematic design and the rest of the analog design is replaced by the analog model. Then, this scaled-down SPICE simulation is performed about 10 times to 100 times faster than full-scale SPICE simulation. The analog model of the focused block is compared with the scaled-down SPICE simulation result and the quality of the model is iteratively enhanced. Hence, the analog model enables both compatible integration and flexible analog design verification. This dissertation contributes to reduce test time and to enhance test quality, and helps to set up efficient production testing flows. Depending on the size and performance of CUT, proper testing schemes can maximize the efficiency of production testing. The topics covered in this dissertation can be used in optimizing the test flow and selecting the final production tests to achieve maximum test capability. In addition, the strategies and benefits of analog behavioral modeling techniques that I implemented are presented, and actual verification cases shows the effectiveness of analog modeling for better quality SoC products. / text

Les assemblages PoP pour « Package on Package » permettent d’augmenter fortement la densité d’intégration des circuits et systèmes microélectroniques, par superposition de plusieurs éléments semi-conducteurs actifs. Les interconnexions internes de ces systèmes sont alors soumises à des contraintes jamais atteintes. Nous avons pu identifier, caractériser, modéliser et simuler les mécanismes de défaillance potentiels propres à ces assemblages, et leur évolution : • Les gauchissements dans la phase d’assemblage du « PoP » et ses contraintes thermomécaniques sont plus importants que ceux de chacun des composants individuels. Un modèle analytique original a été construit et mis en ligne afin d’évaluer a priori ce gauchissement. • Les comportements hygroscopiques et hygromécaniques sont simulés et mesurés par une approche originale. L’assemblage « PoP » absorbe plus d’humidité que la somme des deux composants individuels, mais son gauchissement hygromécanique et ses contraintes hygromécaniques sont moins élevées. • Deux types d’essais de vieillissement accéléré sont réalisés pour étudier la fiabilité du « PoP » assemblé sur circuit imprimé : des cycles thermiques et des tests sous fort courant et température élevée. Dans ces deux types d’essais, l’assemblage d’un composant « top » sur un autre composant « bottom » pour former un PoP augmente les risques de défaillances. • L’évolution de la microstructure selon le type de vieillissement est comparée par des analyses physiques et physico-chimiques. Les fissures sont toujours situées dans l’interface substrat/billes, qui correspond aux zones critiques prédites par les simulations. / The assemblies PoP (Package on Package) can greatly increase the integration density of microelectronic circuits and systems, by vertically combining discrete semiconductor elements. The interconnections of these systems suffer the stresses never reached before. We were able to identify, characterize, model and simulate the potential failure mechanisms of these assemblies and their evolution: • The warpage in the assembly phase and thermomechanical stress of "PoP" are more serious than the individual components. An original analytical model has been built and put online for pre-estimating this warpage. • The hygroscopic and hygromechanical behaviors are simulated and measured by an original method. The assembly "PoP" absorbs more moisture than the sum of the individual components, but its hygromechanical warpage and stress are smaller. • Two types of accelerated aging tests are performed to study the reliability of "PoP" at the board level: the thermal cycling and the testing under current and temperature. In both types of tests, assembly a component "top" on another component "bottom" to form a “PoP” increases the risk of failure. • The microstructure evolution depending on the type of aging is compared by the physical and physico-chemical analysis. The cracks are always located in the interface substrate/balls, which corresponds to the critical areas predicted by the simulations.

Thesis (M.S.)--Rochester Institute of Technology, 2007. / Typescript. Includes bibliographical references (leaves 84-86).

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No. of bitstreams: 1 Fabiano Alex Colling.pdf: 5692188 bytes, checksum: 8354ca65e4e9e9a92a55f10b5e92b187 (MD5) Previous issue date: 2014-11-27 / CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / CNPQ – Conselho Nacional de Desenvolvimento Científico e Tecnológico / FAPERGS - Fundação de Amparo à Pesquisa do Estado do Rio Grande do Sul / FINEP - Financiadora de Estudos e Projetos / NUCMAT - Núcleo de Caracterização de Materiais / Programa de Bolsas de Estudo Talentos Tecnosinos / itt Chip - Instituto Tecnológico de Semicondutores da Unisinos / Hongik University da Coreia do Sul / Modelab - Laboratório de Modelagem Elétrica Térmica e Mecânica de Módulos e Encapsulamentos e Eletrônicos / O desenvolvimento de novas tecnologias de encapsulamento de semicondutores tem diminuído o tamanho das trilhas das placas de circuito impresso em busca da miniaturização. Esta diminuição está chegando ao limite possível de ser construído pelo fato de apresentar problemas, como aumento da resistência, ou por ruptura por eletromigração, além do aumento do custo para o controle de partículas nas salas limpas de fabricação. O Encapsulamento sobre Encapsulamento (Package on Package - PoP) surge como uma proposta de encapsulamento com empilhamento de chips finos para reduzir a ocupação do chip na placa. A diferença de propriedades térmicas e mecânicas dos diferentes materiais que compõem o chip encapsulado pode resultar no empenamento do componente. Neste trabalho, foi simulado o comportamento termomecânico de um dispositivo eletrônico encapsulado pela tecnologia Package on Package. Foi avaliado, do ponto de vista térmico e mecânico, quais são os fatores geradores do empenamento de semicondutores encapsulados com a tecnologia PoP recorrente no processo de moldagem. As condições e parâmetros de processo de fabricação foram estudados durante a fabricação de um protótipo de chip de 40 µm de espessura e moldado com um composto de epóxi do tipo 2 (Epoxy Molding Compound - EMC) realizado no Laboratório de Materiais do Departamento de Ciências dos Materiais e Engenharia da universidade Hongik da Coreia do Sul, parceira no projeto de pesquisa. Através das medições do empenamento, por interferometria de Moiré, realizadas no laboratório de testes da empresa Sul Coreana Hana Micron, foi possível construir correlações com a simulação computacional deste componente. Os resultados desta comparação foram utilizados como base para a validação da simulação e ajustes de dados de entrada utilizados em outras três espessuras diferentes de chip de silício (70, 100 e 200 µm) e dois tipos diferentes de EMC (EMC1 e EMC2). As condições e parâmetros de processo de fabricação, a influência no empenamento das diferentes espessuras e tipos de EMC dos componentes simulados foram avaliados. As simulações realizadas com variação no EMC em componentes com chip de 40 µm mostraram que o EMC do tipo 1 apresenta uma redução de 42,39% no empenamento na parte superior do componente (Top) maior em relação ao EMC do tipo 2. No Top, o substrato com chip de 100 µm, o empenamento foi reduzido em 36,62% e no de 200 µm a redução foi de 3,29%. Os resultados mostram a importância da simulação para prever a tendência do empenamento, quando existe a necessidade de muitas variações de parâmetros de processo de fabricação. / The development of new technologies of semiconductors packaging has reduced the size of the tracks of printed circuit boards in search of miniaturization. This reduction has been reaching its own possible limits (of construction) because it has several problems, such as increase of resistance, rupture by electromigration, in addition to the increase of costs of particles control in manufacturing cleanrooms. Package on Package (PoP) comes as a proposition for encapsulation with thin chips piling in order to reduce chip occupation on the board. The difference in thermal and mechanical properties of the different materials that make up the encapsulated chip may result in the warpage of the component. In this study, the thermomechanical behavior of an electronic device encapsulated by the Package on Package technology was simulated. From the thermal and mechanical point of view, it was evaluated what factors cause the warpage of the semiconductors encapsulated with the PoP technology, warpage which is recurrent in the molding process. The manufacturing process conditions and parameters were assessed/evaluated during the making of a 40μm-thick chip prototype which was molded with a type 2 Epoxi Molding Compound - EMC - in the Materials Laboratory of Hongik University Department of Materials Science and Engineering in South Korea, our partner in this research project. Through the warpage measurements, by Moiré interferometry carried out in South Korean Hana Micron's test laboratory, we managed to build correlations with the computing simulation of this component. The results of this comparison were used as base for validation of the simulation and for adjustment of input data used in three different thickness of silicon chips (70, 100 and 200 μm) and two different EMC (EMC1 and EMC2). The manufacturing process conditions and parameters, the influence in warpage of different thicknesses and simulated components EMC types were evaluated. The simulations carried out with EMC variation in components with 40μm chip demonstrated that type 1 EMC has a decrease in warpage of the upper part of the component (Top) 42.39 percent larger than type 2 EMC. On the Top, the substract plus chip with 100 μm thickness, the warpage was reduced in 36.62 percent, and in the 200 μm chip, the reduction was by 3.29 percent. The results show the importance of simulation to predict warpage tendency, when there is the need for many variations of manufacturing production parameters.

Les assemblages PoP pour " Package on Package " permettent d'augmenter fortement la densité d'intégration des circuits et systèmes microélectroniques, par superposition de plusieurs éléments semi-conducteurs actifs. Les interconnexions internes de ces systèmes sont alors soumises à des contraintes jamais atteintes. Nous avons pu identifier, caractériser, modéliser et simuler les mécanismes de défaillance potentiels propres à ces assemblages, et leur évolution : * Les gauchissements dans la phase d'assemblage du " PoP " et ses contraintes thermomécaniques sont plus importants que ceux de chacun des composants individuels. Un modèle analytique original a été construit et mis en ligne afin d'évaluer a priori ce gauchissement. * Les comportements hygroscopiques et hygromécaniques sont simulés et mesurés par une approche originale. L'assemblage " PoP " absorbe plus d'humidité que la somme des deux composants individuels, mais son gauchissement hygromécanique et ses contraintes hygromécaniques sont moins élevées. * Deux types d'essais de vieillissement accéléré sont réalisés pour étudier la fiabilité du " PoP " assemblé sur circuit imprimé : des cycles thermiques et des tests sous fort courant et température élevée. Dans ces deux types d'essais, l'assemblage d'un composant " top " sur un autre composant " bottom " pour former un PoP augmente les risques de défaillances. * L'évolution de la microstructure selon le type de vieillissement est comparée par des analyses physiques et physico-chimiques. Les fissures sont toujours situées dans l'interface substrat/billes, qui correspond aux zones critiques prédites par les simulations.

End-users often complain about usability and safety problems in consumer packages. This study shows that these issues are an obstacle to the achievement of user satisfaction and to gain a competitive advantage in the market. To this end, a case study on food and beverage packages was done in order to identify and analyze these usability and safety problems based on the lifetime phases of packages in which end-users are involved. The study revealed that safety, clarity, legibility, visibility, storability, openability, re-closability, usefulness, and pleasantness are key areas where problems are widespread and should be considered by package developers and designers. The study also indicated that the problems occurred during use result from insufficiencies in current package design processes. These insufficiencies occur basically in the specification of the context of package use, identification of usability requirements, and the active involvement of the actual users in the package design processes. This study also highlights the need for a user-centered approach to package design in order to overcome the insufficiencies in current package design processes in a structured way and thus to achieve usable and safe packages. In addition, based on the literature and case study findings, checklists for user-centered package design process activities and for the design and evaluation of the packages are included. Moreover, a set of methods to be used during user-centered package design process is recommended.

Magister Scientiae - MSc (Earth Science) / This study area is situated within the Eastern Bushveld complex at Dwarsrivier chrome mine, which is approximately 30 km from Steelpoort and 60km from Lydenburg in the Mpumalanga province. The primary aim of the project is to identify the petrological and geochemical characteristics that can be used to distinguish the various rock types of feldspathic pyroxenites, chromitites, anorthosites and chromitite pyroxenites and determine whether the various rock types are from the MG2 package and MG3 package were formed from a single or multiple magma pulses. The geochemical and mineralogical variation studies were carried out using cores from borehole DWR74 and DWR172 located on the farm Dwarsrivier 372 KT. Using the combination of various multivariate statistical techniques (factor, cluster and discriminant analysis) multi element diagrams and trace element ratios, the outcome of the study demonstrated that each of the four rock types can be sub-divided into two groups.