No description available.

No description available.

No description available.

No description available.

No description available.

No description available.

The goal of this dissertation is to present a systematic approach to integrating the multidisciplinary design process in power electronics through the integration of existing CAD tools, multidisciplinary modeling and system optimization. Two major benefits are expected from the utilization of the proposed integrated design methodology. Firstly, it will significantly speed up the design process and will eliminate errors resulting from repeated manual data entry and information exchange. Secondly, the integrated design optimization will result in better utilization of materials and components. In order to understand the basic relationship between electrical and thermal phenomena, the self-heating effect of a simple copper conductor is modeled analytically. Based on these models, a guideline for copper trace design is proposed. The next step towards developing an integrated design methodology is to create threedimensional solid-body-based models that characterize the electrical, thermal and mechanical properties. The electrical model of an integrated power electronics module (IPEM), including parasitic parameters, is developed and experimentally verified with impedance measurements. Together with the thermal model, it lays the foundation for the integrated electrical and thermal analysis and design. The software integration framework is presented along with the software tools chosen for this study, which include Saber for electrical circuit simulation, Maxwell Q3D Extractor for parameter extraction, and I-DEAS for geometry and thermal modeling. Each of these software tools is controlled via its own macro language files. iSIGHT is then used to interface with these tools in order to achieve software integration. The DC-DC IPEM layout design is investigated and improved upon by using the integrated design methodology. Several examples of parametric study are presented. The first example shows the tradeoff between electrical and thermal performance for different ceramic layer thicknesses of module substrate. The next example looks at the commonmode noise problem that exists in different direct-bonded copper (DBC) layouts. / Ph. D.

To support the study of potential utilization of the emerging silicon carbide (SiC) devices, two SiC active switches, namely 1.2 kV, 5 A SiC JFET manufactured by SiCED, and 1.2 kV, 20 A SiC MOSFET by CREE, have been investigated systematically in this thesis. The static and switching characteristics of the two switches have firstly been characterized to get the basic device information. Specific issues in the respective characterization process have been explored and discussed. Many of the characterization procedures presented are generic, so that they can be applied to the study of any future SiC unipolar active switches. Based on the characterization data, different modeling procedures have also been introduced for the two SiC devices. Considerations and measures about model improvement have been investigated and discussed, such as predicting the MOSFET transfer characteristics under high drain-source bias from switching waveforms. Both models have been verified by comparing simulation waveforms with the experimental results. imitations of each model have been explained as well. In order to capture the parasitic ringing in the very fast switching transients, a modeling methodology has also been proposed considering the circuit parasitics, with which a device-package combined simulation can be conducted to reproduce the detailed switching waveforms during the commutation process. This simulation, however, is inadequate to provide deep insights into the physics behind the ringing. Therefore a parametric study has also been conducted about the influence of parasitic impedances on the device's high-speed switching behavior. The main contributors to the parasitic oscillations have been identified to be the switching loop inductance and the device output junction capacitances. The effects of different parasitic components on the device stresses, switching energies, as well as electromagnetic interference (EMI) have all been thoroughly analyzed, whose results exhibit that the parasitic ringing fundamentally does not increase the switching loss but worsens the device stresses and EMI radiation. Based on the parametric study results, this thesis finally compares the difference of SiC JFET and MOSFET in their respective switching behavior, comes up with the concept of device switching speed limit under circuit parasitics, and establishes a general design guideline for high-speed switching circuits on device selection and layout optimization. / Master of Science

京都大学 / 新制・課程博士 / 博士(理学) / 甲第25144号 / 理博第5051号 / 新制||理||1720(附属図書館) / 京都大学大学院理学研究科生物科学専攻 / (主査)准教授 高山 浩司, 教授 田村 実, 教授 石田 厚 / 学位規則第4条第1項該当 / Doctor of Agricultural Science / Kyoto University / DGAM

This thesis is an investigation of architectural intervention; specifically a question: "How does one mediate the old through the intervention of the new?" By using methods of dissection, one is able to deconstruct the layers of a historic situation and identify key elements of the old in an effort to provoke a dialog with elements of the new. The historic artifact, in this case an abandoned distillery warehouse, held the essential material conditions of a stereotomic mass and a tectonic frame. Through the introduction of a new program, a brewery, a third architectural condition, the parasitic, was deployed to reveal a new synthesized whole. / Master of Architecture