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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Scheduling for a Large-Scale Production System Based on a Continuous and Timed Petri-Net Model

OKUMA, Shigeru, SUZUKI, Tatsuya, INABA, Akio, KIM, YoungWoo 01 March 2003 (has links)
No description available.
2

Performance Modeling And Evaluation Of Network Processors

Govind, S 12 1900 (has links)
In recent years there has been an exponential growth in Internet traffic resulting in increased network bandwidth requirements which, in turn, has led to stringent processing requirements on network layer devices like routers. Present backbone routers on OC 48 links (2.5Gbps) have to process four million minimum-sized packets per second. Further, the functionality supported in the network devices is also on the increase leading to programmable processors, such as Intel's IXP, Motorola's C5 and IBM's.NP. These processors support multiple processors and multiple threads to exploit packet-level-parallelism inherent in network workloads. This thesis studies the performance of network processors. We develop a Petri Net model for a commercial network processors (Intel IXP 2400,2850) for three different applications viz., IPv4 forwarding, Network Address Translation and IP security protocols. A salient feature of the Petri net model is its ability to model the application, architecture and their interaction in great detail. The model is validated using the intel proprietary tool (SDK 3.51 for IXP architecture) over a range of configurations. Our Performance evaluation results indicate that 1. The IXP processor is able to support a throughput of 2.5 Gbps for all modeled applications. 2. Packet buffer memory (DRAM) is the bottleneck resource in a network proces sor and even multithreading is ineffective beyond a total of 16 threads in case of header processing applications and beyond 32 threads for payload processing applications. Since DRAM is the bottleneck resource we explore the benefits of increasing the DRAM banks and other software schemes like offloading the packet header to SRAM. The second part of the thesis studies the impact of parallel processing in network processor on packet reordering and retransmission. Our results indicate that the concurrent processing of packets in a network processor and buffer allocation schemes in TFIFO leads to a significant packet reordering, (61%), on a 10-hop network (with packet sizes of 64 B) which in turn leads to a 76% retransmission under the TCP fast-restransmission algorithm. We explore different transmit buffer allocation schemes namely, contiguous, strided, local, and global for transmit buffer which reduces the packet retransmission to 24%. Our performance results also indicate that limiting the number of microengines can reduce the extent of packet reordering while providing the same throughput. We propose an alternative scheme, Packetsort, which guarantees complete packet ordering while achieving a throughput of 2.5 Gbps. Further, we observe that Packetsort outperforms, by up to 35%, the in-built schemes in the IXP processor namely, Inter Thread Signaling (ITS) and Asynchronous Insert and Synchronous Remove (AISR). The final part of this thesis investigates the performance of the network processor in a bursty traffic scenario. We model bursty traffic using a Pareto distribution. We consider a parallel and pipelined buffering schemes and their impact on packet drop under bursty traffic. Our results indicate that the pipelined buffering scheme outperforms the parallel scheme.
3

Evolution et modélisation de processus biologiques : application à la régulation de la compétence naturelle pour la transformation génétique bactérienne chez les streptocoques / Evolution and modeling of biological processes : application to the regulation of natural competence for bacterial genetic transformation in Streptococci

Weyder, Mathias 29 March 2017 (has links)
Afin de faire face à différents types de stress et s'adapter à de nouveaux environnements, les bactéries ont développé de nombreux mécanismes génétiquement régulés. La compétence pour la transformation naturelle est un processus qui favorise le transfert horizontal de gènes. Si les espèces phylogénétiquement éloignées partagent des mécanismes conservés d'intégration et de remaniement de l'ADN, les circuits de régulation de la compétence ne sont toutefois pas universels mais adaptés au mode de vie de chaque espèce. Chez les bactéries Gram-positives, les cascades de régulation de Streptococcus pneumoniae et Bacillus subtilis sont les mieux documentées. Si de nombreux modèles mathématiques ont été établis pour étudier différents aspects de la régulation des compétences chez B. subtilis, un seul modèle à échelle de population a été développé pour S. pneumoniae, il y a plus de dix ans, sur la base d'hypothèses contestées par de nouvelles données expérimentales. Nous avons développé, chez S. pneumoniae, un modèle fondé sur la connaissance de la régulation de la compétence qui intègre les éléments biologiques essentiels connus à ce jour. La cohérence structurelle de la topologie du réseau est confirmée par le formalisme des réseaux de Petri. Le réseau est ensuite transformé en un ensemble d'équations différentielles ordinaires pour étudier son comportement dynamique. La cinétique des protéines a été estimée en utilisant des données de luminescence et l'estimation des paramètres a été contrainte à partir des connaissances disponibles. Après avoir testé des modèles alternatifs, nous avons proposé l'existence d'un produit de gène tardif supplémentaire pouvant inhiber l'action de ComW, l'activateur du facteur sx. Nous apportons également un nouvel éclairage sur cette cascade de régulation en prédisant la cinétique de composantes du système qui pourraient être impliquées dans des comportements spécifiques. Ce modèle consolide les connaissances expérimentales acquises sur la régulation de la compétence chez S. pneumoniae. De plus, il peut être appliqué aux autres espèces de streptocoques appartenant aux groupes mitis et anginosus puisqu'ils partagent le même circuit régulateur. À l'échelle populationnelle, la transition vers l'état de compétence se produit d'abord dans une sous-population de cellules et se propage ensuite dans toute la population par contact physique cellule à cellule. En permettant la simulation du comportement d'une cellule individuelle, le modèle pourra servir de module dans la conception d'un modèle d'une population bactérienne composée de cellules hétérogènes. / Bacteria have evolved many types of genetically induced mechanisms to face different types of stresses and to adapt to new environments. Competence for natural transformation is one such process that promotes horizontal gene transfer. If phylogenetically distant species share conserved uptake and processing apparatus, competence regulatory circuits are not universal but adapted to every species' lifestyle. In Gram-positive bacteria, Streptococcus pneumoniae and Bacillus subtilis regulatory cascades are the best documented. If many mathematical models have been established to study different aspects of competence regulation in B. subtilis, only one population-scaled model has been developed for S. pneumoniae, a decade ago, based on hypotheses that are challenged by new experimental data. We develop, in S. pneumoniae, a knowledge-based model of the competence regulation at cell level that integrates the enriched biological knowledge acquired to date. The structural consistency of the network topology is confirmed using Petri net formalism. The network is further turned into a set of ordinary differential equations to study its dynamics behavior. Protein kinetics are estimated using time-series luminescence data and other parameter estimations are constrained according to available knowledge. We point out some gap in competence shut-off knowledge, and, after testing alternative models, we predict the requirement of a yet unknown late com gene product inhibiting the action of ComW, the ?x factor activator. We also bring new insights into this regulatory cascade by predicting the system components that might be involved in specific experimental behavior. Our model consolidates the experimental knowledge acquired on competence regulation in S. pneumoniae. Moreover, it can be applied to the other streptococci species belonging to the mitis and anginosus groups since they shared the same regulatory circuit. In the population, the competence shift happens first in a subpopulation of cells and spreads into the whole population through cell to cell contact. Allowing simulation of individual cell behavior, our model will provide a brick for the design of a population-scale model composed of heterogeneous cells.
4

Petri Net Model Based Energy Optimization Of Programs Using Dynamic Voltage And Frequency Scaling

Arun, R 06 1900 (has links) (PDF)
High power dissipation and on-chip temperature limit performance and affect reliability in modern microprocessors. For servers and data centers, they determine the cooling cost, whereas for handheld and mobile systems, they limit the continuous usage of these systems. For mobile systems, energy consumption affects the battery life. It can not be ignored for desktop and server systems as well, as the contribution of energy continues to go up in organizations’ budgets, influencing strategic decisions, and its implications on the environment are getting appreciated. Intelligent trade-offs involving these quantities are critical to meet the performance demands of many modern applications. Dynamic Voltage and Frequency Scaling (DVFS) offers a huge potential for designing trade-offs involving energy, power, temperature and performance of computing systems. In our work, we propose and evaluate DVFS schemes that aim at minimizing energy consumption while meeting a performance constraint, for both sequential and parallel applications. We propose a Petri net based program performance model, parameterized by application properties, microarchitectural settings and system resource configuration, and use this model to find energy efficient DVFS settings. We first propose a DVFS scheme using this model for sequential programs running on single core multiple clock domain (MCD) processors, and evaluate this on a MCD processor simulator. We then extend this scheme for data parallel (Single Program Multiple Data style) applications, and then generalize it for stream applications as well, and evaluate these two schemes on a full system CMP simulator. Our experimental evaluation shows that the proposed schemes achieve significant energy savings for a small performance degradation.

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