ITC/USA 2006 Conference Proceedings / The Forty-Second Annual International Telemetering Conference and Technical Exhibition / October 23-26, 2006 / Town and Country Resort & Convention Center, San Diego, California / Many satellite payloads require wide-band channels for transmission of large amounts of data to users on the ground. These channels typically have substantial distortions, including bandlimiting distortions and high power amplifier (HPA) nonlinearities that cause substantial degradation of bit error rate performance compared to additive white Gaussian noise (AWGN) scenarios. An adaptive equalization algorithm has been selected as the solution to improving bit error rate performance in the presence of these channel distortions. This paper describes the design and implementation of an adaptive baseband equalizer (ABBE) utilizing the latest FPGA technology. Implementation of the design was arrived at by first constructing a high fidelity channel simulation model, which incorporates worst-case signal impairments over the entire data link. All of the modem digital signal processing functions, including multirate carrier and symbol synchronization, are modeled, in addition to the adaptive complex baseband equalizer. Different feedback and feed-forward tap combinations are considered as part of the design optimization.

Στη παρούσα διπλωματική εργασία μελετήθηκε, σχεδιάστηκε, προσομοιώθηκε και κατασκευάστηκε ένα σύστημα ενός ταλαντωτή το οποίο μειώνει τον θόρυβο φάσης (phase noise) σε εικονικά οποιονδήποτε ήδη υπάρχον ταλαντωτή ελεγχόμενου από τάση (VCO). Για να το πετύχει αυτό η προτεινόμενη τεχνική δανείζεται από την ιδέα του βρόχου κλειδωμένης φάσης (Phase Locked Loop) και με λίγα επιπλέον ηλεκτρονικά στοιχεία καθιστά δυνατή την μείωση του phase noise επηρεάζοντας σε μικρό βαθμό τα χαρακτηριστικά του VCO αλλά και δίνοντας την δυνατότητα παραμετροποίησης των χαρακτηριστικών ποιοτικών στοιχείων του τελικού ταλαντωτή που προκύπτει. Το σύστημα του ταλαντωτή κατασκευάστηκε σε πλακέτα(PCB) με διακριτά στοιχεία τα οποία παρέχονταν από το Εργαστήριο Ηλεκτρονικών Εφαρμογών. Το σύστημα αυτό μπορεί να ανταποκριθεί στις ραγδαία αυξανόμενες απαιτήσεις απόδοσης των ταλαντωτών στις σημερινές εφαρμογές, όσο αφορά στον χαμηλό θόρυβο φάσης, την χαμηλή κατανάλωση, την μικρή πολυπλοκότητα στο σχεδιασμό, την μικρή επιφάνεια και την ευκολία στην ολοκλήρωση. / The present diploma thesis pertains the study, design, simulation and implementation of an oscillator system that reduces phase noise in virtually any given already existing voltage controlled oscillator (VCO). To achieve that the proposed technique borrows from the idea of the Phase Locked Loop and with just a few extra electronic components it enables the reduction of phase noise ,by affecting the core characteristic qualities of the employed VCO only by a small fraction, as well as the optimization of the specifications of the resulting oscillator. This oscillator system was manufactured on a printed circuit board and implemented with discrete components which were supplied by the Applied Electronics Lab. This system can measure up to the increasing performance demands for oscillators by todays applications in terms of low phase noise, low power consumption, small design complexity, small area and ease of integration.

Approved for public release, distribution is unlimited / The performance of coherent and noncoherent RAKE receivers over a fading channel in the presence of pulse-noise interference and additive white Gaussian noise is analyzed. Coherent RAKE receivers require a pilot tone for coherent demodulation. Using a first order phase-lock-loop to recover a pilot tone with additive white Gaussian noise causes phase distortions at the phase-lock-loop output, which produce an irreducible phase noise error floor for soft decision Viterbi decoding. Both coherent and noncoherent RAKE receivers optimized for additive white Gaussian noise perform poorly when pulse-noise interference is present. When soft decision convolutional coding is considered, the performance degrades as the duty cycle of the pulse-noise interference signal decreases. The reverse is true for hard decision Viterbi decoding, since fewer bits experience interference and bit errors with high noise variance cannot dominate the decision statistics. Soft decision RAKE receiver optimized for pulse-noise interference and additive white Gaussian noise performed the best for both the coherent and noncoherent RAKE receivers. This receiver scales the received signal by the inverse of the variance on a bit-by-bit basis to minimize the effect of pulse-noise interference. The efficacy is demonstrated by analytical results, which reveal that this receiver reduces the probability of bit error down to the irreducible phase noise error floor when pulse-noise interference is present. This demonstrates how important it is to design the receiver for the intended operational environment. / Civilian, Department of Defense

The expanding growth of mobile products and services has led to various wireless communication standards that employ different spectrum bands and protocols to provide data, voice or video communication services. Software deffned radio and cognitive radio are emerging techniques that can dynamically integrate various standards to provide seamless global coverage, including global roaming across geographical regions, and interfacing with different wireless networks. In software deffned radio and cognitive radio, one of the most critical RF blocks that need to exhibit frequency agility is the phase lock loop (PLL) frequency synthesizer. In order to access various standards, the frequency synthesizer needs to have wide frequency tuning range, fast tuning speed, and low phase noise and frequency spur. The traditional analog charge pump frequency synthesizer circuit design is becoming diffcult due to the continuous down-scalings of transistor feature size and power supply voltage. The goal of this project was to develop an all digital phase locked loop (ADPLL) as the alternative solution technique in RF transceivers by taking advantage of digital circuitry's characteristic features of good scalability, robustness against process variation and high noise margin. The targeted frequency bands for our ADPLL design included 880MHz-960MHz, 1.92GHz-2.17GHz, 2.3GHz-2.7GHz, 3.3GHz-3.8GHz and 5.15GHz-5.85GHz that are used by wireless communication standards such as GSM, UMTS, bluetooth, WiMAX and Wi-Fi etc. This project started with the system level model development for characterizing ADPLL phase noise, fractional spur and locking speed. Then an on-chip jitter detector and parameter adapter was designed for ADPLL to perform self-tuning and self-calibration to accomplish high frequency purity and fast frequency locking in each frequency band. A novel wide band DCO is presented for multi-band wireless application. The proposed wide band adaptive ADPLL was implemented in the IBM 0.13µm CMOS technology. The phase noise performance, the frequency locking speed as well as the tuning range of the digitally controlled oscillator was assessed and agrees well with the theoretical analysis.

This dissertation considers three related problems in distributed transmission and reception networks. Generally speaking, these types of networks have a transmit cluster with one or more transmit nodes and a receive cluster with one or more receive nodes. Nodes within a given cluster can communicate with each other using a wired or wireless local area network (LAN/WLAN). The overarching goal in this setting is typically to increase the efficiency of communication between the transmit and receive clusters through techniques such as distributed transmit beamforming, distributed reception, or other distributed versions of multi-input multi-output (MIMO) communication. More recently, the problem of wireless power transfer has also been considered in this setting. The first problem considered by this dissertation relates to distributed reception in a setting with a single transmit node and multiple receive nodes. Since exchanging lightly quantized versions of in-phase and quadrature samples results in high throughput requirements on the receive LAN/WLAN, previous work has considered an approach where nodes exchange hard decisions, along with channel magnitudes, to facilitate combining similar to an ideal receive beamformer. It has been shown that this approach leads to a small loss in SNR performance, with large reductions in required LAN/WLAN throughput. A shortcoming of this work, however, is that all of the prior work has assumed that each receive node has a perfect estimation of its channel to the transmitter. To address this shortcoming, the first part of this dissertation investigates the effect of channel estimation error on the SNR performance of distributed reception. Analytical expressions for these effects are obtained for two different modulation schemes, M-PSK and M2-QAM. The analysis shows the somewhat surprising result that channel estimation error causes the same amount of performance degradation in ideal beamforming and pseudo-beamforming systems despite the fact that the channel estimation errors manifests themselves quite differently in both systems. The second problem considered in this dissertation is related to oscillator stability and phase noise modeling. In distributed transmission systems with multiple transmitters in the transmit cluster, synchronization requirements are typically very strict, e.g., on the order of one picosecond, to maintain radio frequency phase alignment across transmitters. Therefore, being able to accurately model the behavior of the oscillators and their phase noise responses is of high importance. Previous approaches have typically relied on a two-state model, but this model is often not sufficiently rich to model low-cost oscillators. This dissertation develops a new three-state oscillator model and a method for estimating the parameters of this model from experimental data. Experimental results show that the proposed model provides up to 3 dB improvement in mean squared error (MSE) performance with respect to a two-state model. The last part of this work is dedicated to the problem of wireless power transfer in a setting with multiple nodes in the transmit cluster and multiple nodes in the receive cluster. The problem is to align the phases of the transmitters to achieve a certain power distribution across the nodes in the receive cluster. To find optimum transmit phases, we consider a iterative approach, similar to the prior work on one-bit feedback for distributed beamforming, in which each receive node sends a one-bit feedback to the transmit cluster indicating if the received power in that time slot for that node is increased. The transmitters then update their phases based on the feedback. What makes this problem particularly interesting is that, unlike the prior work on one-bit feedback for distributed beamforming, this is a multi-objective optimization problem where not every receive node can receive maximum power from the transmit array. Three different phase update decision rules, each based on the one-bit feedback signals, are analyzed. The effect of array sparsity is also investigated in this setting.

In the design of voltage-controlled oscillators (VCOs) for communication systems, timing jitter is of major concern since it is the largest contributor to the bit-error rate. The latest deep submicron processes provide the possibility of higher oscillator speed at the cost of increased device noise and a higher 1/f noise corner. Therefore it is crucial to characterize the upconverted 1/f noise for practical applications. This dissertation presents a simple model to relate the time domain jitter and frequency domain phase noise in the presence of non-negligible 1/f noise sources. It will simplify the design, simulation, and testing of the PLL, since with this technique only the open loop VCO needs to be considered. Design methodologies for white noise dominated ring oscillators and PLLs are also developed by analyzing the upconverted thermal noise in time domain using a LTI model. The trade-off and relationship between jitter, speed, power dissipation and VCO geometry are evaluated for different applications. This model is supported by the measured data from 24 ring oscillators with different geometry fabricated in TSMC 0.18um process. The theory developed in this dissertation is applied to the design of PLL- and DLL- based true random number generators (TRNG) for application in the area of“smart cards". New architectures of dual-oscillator sampling and delay-line sampling are proposed for random number generation, which has the advantage of lower power dissipation and lower cost over traditional approaches. Both structures are implemented in test chips fabricated in AMI 1.5um process. The PLL-based TRNG passed the NIST SP800-22 statistical test suite and the DLL-based TRNG passed both the NIST SP800-22 statistical test suite and the Diehard battery of tests.

As Moore���s Law continues to give rise to ever shrinking channel lengths, circuits are becoming more digital and ever increasingly faster. Generating high frequency clocks in such scaled processes is becoming a tough challenge. Digital phase locked loops (DPLLs) are being explored as an alternative to conventional analog PLLs but suffer from issues such as low bandwidth and higher quantization noise. A digital multiplying delay locked loop (DMDLL) is proposed which aims at leveraging the benefit of high bandwidth of DLL while at the same time achieving the frequency multiplication property of PLL. It also offers the benefits of easier portability across process and occupies lesser area. The proposed DMDLL uses a simple flip-flop as 1-bit TDC (Time Digital Converter) for Phase Detector (PD). A digital accumulator acts as integrator for loop filter while a ��-�� DAC in combination with a VCO acts like a DCO. A carefully designed select logic in conjunction with a MUX achieves frequency multiplication. The proposed digital MDLL is taped out in 130nm process and tested to obtain 1.4GHz output frequency with 1.6ps RMS jitter, 17ps peak-to-peak jitter and -50dbC/Hz reference spurs. / Graduation date: 2012

The objective of this research is to demonstrate the feasibility of the implementation of wideband RF CMOS PLLs with high spectral purity using deep sub-micron technologies. To achieve wide frequency coverage, this dissertation proposed a 45-nm SOI-CMOS RF PLL with a wide frequency range to support multiple standards. The PLL has small parasitic capacitance with the help of a SOI technology, increasing the frequency tuning range of a capacitor bank. A designed and fabricated chip demonstrates the PLL supporting almost all cellular standards with a single PLL. This dissertation also proposed a third order sample-hold loop filter with two MOS switches for high spectral purity. Sample-hold operation improves in-band and out-of-band phase noise performance simultaneously in RF PLLs. By controlling the size of the MOS switches and control time, the nonideal effects of the MOS switches are minimized. The sample-hold loop filter is implemented within a 45-nm RF PLL and the performance is evaluated. Thus, this research provides a solution for wideband CMOS frequency synthesizers for multi-band, multi-mode, and multiple-standard applications in deep sub-micron technologies.

The objective of the proposed research is to develop novel, fully-packaged voltage controlled oscillators (VCOs), concurrent oscillators, and multi-mode filters using Liquid Crystalline Polymer (LCP) dielectric material that are directly applicable to simultaneous multi-band radio communication. Integrated wireless devices of the near-future will serve more diverse range of applications (computing, voice/video/data communication) and hence, will require more functionality. This research is focused on providing cost-effective and area-efficient solutions for multi-band/multi-mode oscillators and filters using system-on-package (SOP) design methodology. Silicon-based integrated circuits (ICs) provide an economical method of miniaturizing modules and hence, are attractive for multi-band applications. However, fully monolithic solutions are limited, by its high substrate losses, and marginal quality factors (Qs) of the passives, to low profile applications. Furthermore, the VCOs made on conventional packaging technologies are not very cost-effective. This thesis is directed towards developing highly optimized VCOs and filters using LCP substrate for use in multi-mode radio systems. The thesis investigates and characterizes lumped passive components on new LCP based technology feasible for VCO and filter design. The dissertation then investigates design techniques for optimizing both power consumption and the phase noise of the VCOs to be employed in commercial wireless systems. This work then investigates the temperature performance of LCP-based VCOs satisfying military standards. Another aspect of the thesis is the development of dual-band (multi-mode) oscillators. The approach is to employ existing multi-band theories to demonstrate one of the first prototypes of the oscillator. Finally, the design of multi-mode, lumped-element type filters was investigated.

The wavelength-division multiplexing (WDM) is a well know technique capable of increasing the total capacity of a lightwave communication system; however, the system performance can be significantly limited by the dispersive and nonlinear effects, among others. This dissertation is mainly focused on the nonlinear effects upon the short-haul and long-haul lightwave systems.The short-haul lightwave system is mainly adopted in the access network. A passive optical access network is generally used to connect individual homes to a central office of a local area, and since there is no active component installed outside the central office of the passive optical access network, the system complexity and maintenance frequency can be significantly reduced. This dissertation provides a long-reach passive optical network (LR-PON) which can further reduce the system complexity and system cost. We found that four-wave mixing (FWM) and Rayleigh backscattering induced crosstalk were two main reasons to degrade the transmission performance in our proposed LR-PON. The long-haul lightwave system is mainly adopted in the transoceanic application. Although differential phase-shit keying (DPSK) modulation format has been confirmed to be suitable for long-haul WDM system, we found that a performance dip can be observed near the system zero dispersion avelength. In this dissertation, we designed various experiments to confirm the nonlinear effect to cause the performance dip being observed, and concluded that self-phase modulation (SPM) was the dominant reason to cause the performance dip rather than cross-phase modulation (XPM) or nonlinear phase noise.