Synchronization is a challenging but very important task in communications. In digital communication systems, a hierarchy of synchronization problems has to be considered: carrier synchronization, symbol timing synchronization and frame synchronization. For bandwidth efficiency and burst transmission reasons, the former two synchronization steps tend to favor non-data aided (NDA or blind) techniques, while in general, the last one is usually solved by inserting repetitively known bits or words into the data sequence, and is referred to as a data-aided (DA) approach. Over the last two decades, extensive research work has been carried out to design nondata-aided timing recovery and carrier synchronization algorithms. Despite their importance and spread use, most of the existing blind synchronization algorithms are derived in an ad-hoc manner without exploiting optimally the entire available statistical information. In most cases their performance is evaluated by computer simulations, rigorous and complete performance analysis has not been performed yet. It turns out that a theoretical oriented approach is indispensable for studying the limit or bound of algorithms and comparing different methods. The main goal of this dissertation is to develop several novel signal processing frameworks that enable to analyze and improve the performance of the existing timing recovery and carrier synchronization algorithms. As byproducts of this analysis, unified methods for designing new computationally and statistically efficient (i.e., minimum variance estimators) blind feedforward synchronizers are developed. Our work consists of three tightly coupled research directions. First, a general and unified framework is proposed to develop optimal nonlinear least-squares (NLS) carrier recovery scheme for burst transmissions. A family of blind constellation-dependent optimal "matched" NLS carrier estimators is proposed for synchronization of burst transmissions fully modulated by PSK and QAM-constellations in additive white Gaussian noise channels. Second, a cyclostationary statistics based framework is proposed for designing computationally and statistically efficient robust blind symbol timing recovery for time-selective flat-fading channels. Lastly, dealing with the problem of frame synchronization, a simple and efficient data-aided approach is proposed for jointly estimating the frame boundary, the frequency-selective channel and the carrier frequency offset.

International Telemetering Conference Proceedings / October 30-November 02, 1989 / Town & Country Hotel & Convention Center, San Diego, California / The Naval Ocean Research and Development Activity (NORDA) has adapted the Loral Instrumentation Advanced Decommutation system (ADS 100) as a portable maintenance system for one of its remotely deployable buoy systems. This particular buoy system sends up to 128 channels of amplified sensor data to a centralized A/D for formatting and storage on a high density digital recorder. The resulting tapes contain serial PCM data in a format consistent with IRIG Standard 106-87. Predictable and correctable perturbations exist within the data due to the quadrature multiplexed telemetry system. The ADS 100 corrects for the perturbations of the telemetry system and provides the user with diagnostic tools to examine the stored data stream and determine the operational status of the buoy system prior to deployment.

International Telemetering Conference Proceedings / October 30-November 02, 1989 / Town & Country Hotel & Convention Center, San Diego, California / The Naval Ocean Research and Development Activity (NORDA) has adapted the Loral Instrumentation Advanced Decommutation system (ADS 100) as a portable maintenance system for one of its remotely deployable buoy systems. This particular buoy system sends up to 128 channels of amplified sensor data to a centralized A/D for formatting and storage on a high density digital recorder. The resulting tapes contain serial PCM data in a format consistent with IRIG Standard 106-87. Predictable and correctable perturbations exist within the data due to the quadrature multiplexed telemetry system. The ADS 100 corrects for the perturbations of the telemetry system and provides the user with diagnostic tools to examine the stored data stream and determine the operational status of the buoy system prior to deployment.

This thesis proposes a blind receiver for the Nyquist pulse shaped quadratureamplitude modulation (QAM) signals. The focus is on single carrier signals. The blind receiver includes the estimation of the symbol rate, the roll-off factor of the filter, the optimal sample phase, the frequency offset, the phase offset and as well as the correction of frequency and phase offsets. The blind receiver is proposed for the cognitive radio applications. Cognitive radios are intelligent devices which can adapt themselves according to its user and its environment, i.e. they are aware of the user and the environment. Another importance of cognitive radios is they can detect the incoming signal and demodulate it and also respond to the transmitting node with the same parameters. In order to demodulate the signal and to respond the transmitter node, there are some parameters which are needed to be known. The estimation starts with the bandwidth and carrier frequency, continued by the estimation of the symbol rate, which is a crucial factor. After the estimation and restrictions of these parameters, the roll-off factor of the filter is estimated for match filtering to remove the inter symbol interference (ISI) effect. Then the optimal sample phase is detected and the signal is downsampled. The following procedures include the modulation identification and estimation and correction of both frequency and phase offsets. The estimation algorithms performance is compared to the performances of the other algorithms available in the literature. These simulation results are presented and discussed in this thesis.

This thesis presents the analysis, design and characterization of an integrated high-frequency phase-locked loop (PLL) frequency multiplier. The frequency multiplier is novel in its use of a low multiplication factor of 4 and a fully differential topology for rejection of common mode interference signals. The PLL is composed of a voltage controlled oscillator (VCO), injection-locked frequency divider (ILFD) for the first divide-by-two stage, a static master-slave flip-flop (MSFF) divider for the second divide-by-two stage and a Gilbert cell mixer phase detector (PD). The circuit has been fabricated using a standard CMOS 0.18-um process based on its relatively low cost and ready availability. The PLL frequency multiplier generates an output signal at 26 GHz and is the highest operational frequency PLL in the technology node reported to date. Time domain phase plane analysis is used for prediction of PLL locking range based on initial conditions of phase and frequency offsets. Tracking range of the PLL is limited by the inherent narrow locking range of the ILFD, and is confirmed via experimental results. The performance benefits of the fully differential PLL are experimentally confirmed by the injection of differential- and common-mode interfering signals at the VCO control lines. A comparison of the common- and differential-mode modulation indices reveals that a common mode rejection ratio (CMRR) of greater than 20 dB is possible for carrier offset frequencies of less than 1 MHz. Closed-loop frequency domain transfer functions are used for prediction of the PLL phase noise response, with the PLL being dominated by the reference and VCO phase noise contributions. Regions of dominant phase noise contributions are presented and correlated to the overall PLL phase noise performance. Experimental verifications display good agreement and confirm the usefulness of the techniques for PLL performance prediction. The PLL clock multiplier has an operational output frequency of 26.204 to 26.796 GHz and a maximum output frequency step of 16 MHz. Measured phase noise at 1 MHz offset from the carrier is -103.9 dBc/Hz. The PLL clock multiplier core circuit (VCO/ILFD/MSFF Divider/PD) consumes 186 mW of combined power from 2.8 and 4.3 V DC rails. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2009-04-24 11:31:35.384