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In this study, delay-insensitive asynchronous circuit design style has been adopted to systolic array architectures to exploit the benefits of both techniques for improved throughput. A delay-insensitivity verification analysis method employing symbolic delays is proposed for bit-level pipelined asynchronous circuits. The proposed verification method allows datadependent early output evaluation to co-exist with robust delay-insensitive circuit behavior in pipelined architectures such as systolic arrays. Regardless of the length of the pipeline, delay-insensitivity verification of a systolic array with early output evaluation paths in onedimension is reduced to analysis of three adjacent systoles for eight possible early/late output evaluation scenarios. Analyzing both combinational and sequential parts concurrently, delay-insensitivity violations are located and corrected at structural level, without diminishing the early output evaluation benefits. Since symbolic delays are used without imposing any timing constraints on the environment / the method is technology independent and robust against all physical and environmental variations. To demonstrate the verification method, adders are selected for being at the core of data processing systems. Two asynchronous adder topologies in the delay-insensitive dual-rail threshold logic style, having data-dependent early carry evaluation paths, are converted into bit-level pipelined systolic arrays. On these adders, data-dependent delay-insensitivity violations are detected and resolved using the proposed verification technique. The modified adders achieved the targeted O(log2n) average completion time and -as a result of bit-level pipelining- nearly constant throughput against increased bit-length. The delay-insensitivity verification method could further be extended to handle more early output evaluation paths in multi-dimension.

A análise em tempo real de pares de imagens estereoscópicas para extração de características dimensionais da cena tem apresentado crescente interesse, possibilitando robusta navegação robótica e identificação de objetos em cenários dinâmicos. A presente dissertação propõe um método que emprega a análise pixel a pixel e observação de janelas, em pares de imagens estereoscópicas, para extração de denso mapa de disparidades. A arquitetura de processamento proposta é única em sua constituição, misturando elementos de processamento concorrente e seqüencial. O algoritmo estrutura-se em processamento pipeline, permitindo sua implementação em dispositivos de lógica programável e obtenção de resultados em tempo real. / Real-time analysis of stereo images for extraction of dimensional features has been focus of great interest, providing means for autonomous robot navigation and identification of objects in dynamic environments. This work describes a method based in pixel-to-pixel and windows based matching analysis, in stereo images, for constructing dense disparity maps. The proposed processing structure is unique, mixing concurrent and sequential elements. Pipelines structure is employed, targeting implementation in FPGA devices and enabling real-time results.

A análise em tempo real de pares de imagens estereoscópicas para extração de características dimensionais da cena tem apresentado crescente interesse, possibilitando robusta navegação robótica e identificação de objetos em cenários dinâmicos. A presente dissertação propõe um método que emprega a análise pixel a pixel e observação de janelas, em pares de imagens estereoscópicas, para extração de denso mapa de disparidades. A arquitetura de processamento proposta é única em sua constituição, misturando elementos de processamento concorrente e seqüencial. O algoritmo estrutura-se em processamento pipeline, permitindo sua implementação em dispositivos de lógica programável e obtenção de resultados em tempo real. / Real-time analysis of stereo images for extraction of dimensional features has been focus of great interest, providing means for autonomous robot navigation and identification of objects in dynamic environments. This work describes a method based in pixel-to-pixel and windows based matching analysis, in stereo images, for constructing dense disparity maps. The proposed processing structure is unique, mixing concurrent and sequential elements. Pipelines structure is employed, targeting implementation in FPGA devices and enabling real-time results.

In all of the previous pipelining methods such as conventional pipelining, wave pipelining, and mesochronous pipelining, a data wave propagating on the combinational circuit is sampled whenever it arrives to a synchronization stage. In this study, a new wave-pipelining methodology named as Wave Component Sampling Method (WCSM), is proposed. In this method, only the component of a wave, whose maximum and minimum delay difference exceeds the tolerable value, is sampled, and the other components continue to propagate on the circuit. Therefore, the total number of registers required for synchronization decreases significantly. For demonstrating the effectiveness of the proposed WCSM, an 8x8 bit carry save In all of the previous pipelining methods such as conventional pipelining, wave pipelining, and mesochronous pipelining, a data wave propagating on the combinational circuit is sampled whenever it arrives to a synchronization stage. In this study, a new wave-pipelining methodology named as Wave Component Sampling Method (WCSM), is proposed. In this method, only the component of a wave, whose maximum and minimum delay difference exceeds the tolerable value, is sampled, and the other components continue to propagate on the circuit. Therefore, the total number of registers required for synchronization decreases significantly. For demonstrating the effectiveness of the proposed WCSM, an 8x8 bit carry save adder (CSA) multiplier is implemented using 0.18&micro / m CMOS technology. A generic transmission gate logic block with optimized output delay variation depending on the input pattern is designed and used in all of the sub blocks of the multiplier. Post layout simulation results show that, this multiplier can operate at a speed of 3GHz, using only 70 latches. Comparing with the mesochronous pipelining scheme, the number of the registers is decreased by 41% and the total power of the chip is also decreased by 9.5% without any performance loss. An ultra high speed full pipelined CSA multiplier with an operating frequency of 5GHz is also implemented with WCSM. The number of registers is decreased by 45%, and the power consumption of the circuit is decreased by 18.4% comparing with conventional or mesochronous pipelining methods. WCSM is also applied to different multiplier structures employing booth encoders, Wallace trees, and carry look-ahead adders. Comparing full pipelined 8x8 bit WCSM multiplier with the conventional pipelined multiplier, the number of registers in the implementation of booth encoder, Wallace tree, and carry look-ahead adder is decreased by 30%, 51%, and %62, respectively.