Made available in DSpace on 2014-10-09T12:35:49Z (GMT). No. of bitstreams: 0 / Made available in DSpace on 2014-10-09T14:03:46Z (GMT). No. of bitstreams: 0 / Dissertação (Mestrado) / IPEN/D / Instituto de Pesquisas Energeticas e Nucleares - IPEN-CNEN/SP

Made available in DSpace on 2014-10-09T12:35:49Z (GMT). No. of bitstreams: 0 / Made available in DSpace on 2014-10-09T14:03:46Z (GMT). No. of bitstreams: 0 / Embora a terapia com uso de laser de baixa potência (TLBP) seja uma modalidade terapêutica amplamente estudada no meio científico, sua aplicação na clínica médica ainda gera controvérsias, já que a literatura reporta que a TLBP é capaz de promover a proliferação e diferenciação de células tumorais. O objetivo deste estudo foi avaliar os efeitos da TLBP no crescimento celular usando como modelo a linhagem B16F10 de melanoma murino em estado de homeostase e estado redox, além de verificar o comportamento quimiotáxico da linhagem B16F10 por meio do ensaio de migração transwell em resposta à TLBP em diferentes densidades de energia. Foram montados cinco grupos experimentais utilizando um laser de emissão vermelha em λ = 660 nm: Grupo controle (GC) onde nenhuma irradiação foi realizada; G30 (30J/cm2); G60 (60J/cm2); G90 (90J/cm2); G120 (120J/cm2); G150 (150J/cm2), com as respectivas doses utilizadas. Todos os experimentos foram realizados em triplicata e os resultados obtidos foram submetidos à análise estatística. Sob as condições experimentais deste estudo, nossos resultados mostram que a TLBP neste comprimento de onda não promoveu mudanças no metabolismo celular nos tempos de 48 h e 72 h, independente do estado nutricional. Foi possível observar mudança no padrão de comportamento quimiotáxico da linhagem celular B16F10 irradiadas com laser de emissão vermelha. / Dissertação (Mestrado) / IPEN/D / Instituto de Pesquisas Energeticas e Nucleares - IPEN-CNEN/SP

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Made available in DSpace on 2014-10-09T12:50:30Z (GMT). No. of bitstreams: 0 / Made available in DSpace on 2014-10-09T13:58:49Z (GMT). No. of bitstreams: 1 00045.pdf: 1150397 bytes, checksum: fd8a86947b37fabf9aa8ff7b1e99d2a9 (MD5) / Dissertacao (Mestrado) / IEA/D / Escola Politecnica, Universidade de Sao Paulo - POLI/USP

Traction inverter, as a critical component in electrified transportation, has been the subject of many research studies in terms of topologies, modulation, and control schemes. Recently, some of the well-known electric vehicle manufacturers have utilized higher-voltage batteries to benefit from lower current, higher power density, and faster charging times. With the ongoing trend toward higher voltage DC-link in electric vehicles, some multilevel structures have been investigated as a feasible and efficient option for replacing the two-level inverters. Higher efficiency, higher power density, better waveform quality, and inherent fault-tolerance are the foremost advantages of multilevel inverters which make them an attractive solution for this application. The first contribution of this thesis is to investigate and present a comprehensive review of the multilevel structures in traction applications. Secondly, this thesis proposes an electro-thermal model based on foster equivalent thermal networks for a designed three-level active neutral point clamped (ANPC) inverter, as well as a modified sinusoidal pulse-width modulation (SPWM) -based technique. This electro-thermal model and the modulation technique enable temperature estimation in the inverter and minimization of the hotspot temperature and hence, increase the power density. Based on the experimental results derived from the implemented setup, a 12% increase in power density is achieved with the proposed technique. The other contribution is a reduced-complexity model-predictive controller (MPC) for the three-level ANPC inverter without weighting factors in which the number of calculations has dropped from 27 to 12 in each sampling period. The improvements to the structure and control system of the inverter are supported by theoretical analysis, simulation results, and experimental tests. A three-level inverter is implemented for 800 V, 70 kW operation and tested. 750 V Silicon Carbide (SiC) switches are utilized in the inverter structure. Finally, future trends and suggestions for the following studies are stated in this thesis. / Thesis / Doctor of Philosophy (PhD)

DC/DC Power converter design has been following a trend of reducing size while also increasing performance for the last several years. This push for higher power output and smaller footprint and profile requires integration and higher switching frequencies in order to continue. Higher frequencies require physical integration to eliminate problems induced by parasitics, which increase losses. GE's Power Overlay and Philip's PCB integration schemes have been clear steps in the quest to reduce size with new system design techniques. However, both have downsides. GE Power Overlay embeds the devices inside a milled AlN ceramic cavity and then layers interconnections on top using polyimide dielectric interlayers. The milling of AlN ceramic is a very costly and time consuming task due to the brittleness of the material, and the interlayers add additional complexity to the fabrication process. Philip's PCB integration was primarily aimed at integrating passives along with the PCB process for reduction of size. Inductor windings and capacitive layers were built up along with FR4 epoxy layers using typical PCB fabrication methods. However, unlike GE's Power Overlay, the substrate material was several times lower in thermal conductivity which invariably has corresponding thermal penalties. The work presented here reconciles the good of both integration techniques. Initially called Embedded Power, alumina ceramic was used as the substrate and rather than milling holes for the devices, holes were laser cut all the way through and interconnections were made by using interlayers and sputtered copper deposition, similar to GE's method. Integration of passives was done using LTCC ferrite to make an inductor of thin profile, rather than embedding cores and windings inside PCB. However, fabrication remained time consuming due to numerous solder masking and sputtering steps and thermal performance was not optimized due to the use of alumina ceramic. A revised design method called Stacked Power is presented in this dissertation that follows on the work of Embedded Power, but improves on it by simplifying fabrication through the elimination of thermally-restrictive interlayers, as well as time consuming sputtering and electroplating of copper interconnections. Instead, AlN Direct Bonded Copper is used as a multifunctional material thanks to its many-times-greater thermal conductivity than PCB or alumina, solderable device dies are implemented in a vertical fashion, and interconnections are simply made using copper straps soldered into place. For applications where moisture contamination and breakdown isolation are potential problems, dip conformal coating can easily be applied, replacing laborious solder masking. The work in this dissertation describes the fabrication methodology for Stacked Power, demonstrates the thermal advantages, and shows examples of high-frequency buck converters that achieve super-high levels of power density in the smallest of volumes and require no more thermal management than modest airflow. The added cost incurred with aluminum nitride is traded for distinct advantages in terms of low-profile, low airflow requirements for the power output, capability of natural convection for use in locations where fans are prohibitive and compact size for ease of implementation. / Ph. D.

Over the past several years, energy efficiency and power density have become the top concerns for power conversion. Rising energy intensity leads to a higher cost of delivering power. Meanwhile, the demand for compact power supplies grows significantly. It requires power supplies with high efficiency, low profile and high power density. Dc-dc power conversion has been widely applied for industry, medial, military and airspace applications. Conventional PWM dc-dc converters have relatively low power transfer efficiency and low power density. In contrast, resonant dc-dc converters have numerous advantages for dc-dc power conversions. In this work, topologies and system optimization of resonant converters are investigated to meet challenges of high efficiency, high power density, low EMI, easy startup and over current protection. LLC resonant converters can achieve zero-voltage-switching (ZVS) for primary side devices and zero-current-switching (ZCS) for the secondary side rectifiers. The switching loss is minimized. LLC is very attractive to overcome the issues of conventional circuits. However, challenges still remain. First of all, for low-voltage high-current applications, the synchronous rectifier (SR) with lower conduction loss is a must for high efficiency. To solve the driving issues of SRs, a novel synchronous driving scheme is proposed. Experimental results demonstrate the considerable loss reduction with utilization of the proposed driving scheme. Secondly, dc-dc converters are required to meet EMI standard. This work proposes an EMI mode. Based on the proposed model, EMI analysis and noise attenuation techniques are proposed and verified by experiments. Thirdly, startup and over-load protection are another issues of LLC resonant converters. With proposed multi-element resonant converters, the current limit issues can be resolved. In addition, the proposed multi-element resonant converters can utilize higher-order harmonics to enhance power transfer. Fourthly, for high-current applications, the secondary side structure becomes very critical. An improved secondary side construction is proposed to alleviate ac termination losses and SR paralleling issues. Novel winding structures are proposed to reduce the winding loss. The magnetic integration technique is proposed and analyzed, and an optimal integrated transformer design is proposed, which has low loss and compact size. / Ph. D.

Since future microprocessors will have higher current in accordance with Moore's law, there are still challenges for voltage regulators (VRs). Firstly, high efficiency is required not only for easy thermal management, but also for saving on electricity costs for data centers, or battery life extension for laptop computers. At the same time, high power density is required due to the increased power of the microprocessors. This is especially true for data centers, since more microprocessors are required within a given space (per rack). High power density is also required for laptop computers to reduce the size and the weight. To improve power density, a high frequency is required to shrink the size of the output inductors and output capacitors of the multi-phase buck VR. It has been demonstrated that the output bulk capacitors can be eliminated by raising the VR control bandwidth to around 350kHz. Assuming the bandwidth is one-third of the switching frequency, a VR should run at 1MHz to ensure a small size. However, the efficiency of a 12V VR is very poor at 1MHz due to high switching losses. As a result, a 12V VR can only run at 300kHz to 600kHz, and the power density is very low. To attain high efficiency and high power density at the same time, two-stage power architecture was proposed. The concept is "Divide and Conquer". A single-stage VR is split into two stages to get better performance. The second stage has about 5V-6V input voltage; thus the duty cycle can be extended and the switching losses are greatly reduced compared with a single-stage VR. Moreover, a sub-20V MOSFET can be used to further improve the efficiency at high frequencies. The first stage of the proposed two-stage architecture is converting 12V to 5-6V. High efficiency is required for the first stage since it is in series with the second stage. Previous first stage which is a buck converter has good efficiency but bulky size due to low frequency operation. Another problem with using a buck converter is that light-load efficiency of the first stage is poor. To solve these problems, switched-capacitor voltage dividers are proposed. Since the first stage does not require voltage regulation, the sweet point for the voltage divider can be determined and high efficiency can be achieved. At the same time, since there are no magnetic components for the switched-capacitor voltage divider, high power density can be achieved. By very careful design, a power density of more than 2000W/in3 with more than 97% efficiency can be achieved for the proposed voltage divider. The light-load efficiency of the voltage divider can be as high as 99% by reducing the switching frequency at light load. As for the second stage, different low-voltage devices are evaluated, and the best device combinations are found for high-frequency operation. It has been demonstrated that 91% efficiency can be achieved with 600kHz frequency, and 89% efficiency can be achieved with a 1MHz frequency for the second stage. Moreover, adaptive on-time control method and a non-linear inductor structure are proposed to improve CCM and DCM efficiency for the second stage respectively. Previously the two-stage VR was only used as a CPU VR. The two-stage concept can also be applied to other systems. In this dissertation, the two-stage power architecture is applied to two different applications: laptop computers and high-end server microprocessors. The common characteristics of the two applications are their thermal design power (TDP) requirement. Thus the first stage can be designed with much lower power than the maximum system power. It has been demonstrated that the two-stage power architecture can achieve either higher efficiency or higher power density and a lower cost when compared with the single-stage VR. To get higher efficiency, a parallel two-stage power architecture, named sigma architecture, is proposed for VR applications. The proposed sigma VR takes advantage of the high-efficiency, fast-transient unregulated converter (DCX) and relies on this converter to deliver most of the output power, while using a low-power buck converter to achieve voltage regulation. Both the DCX converter and the buck converter can achieve around 90% efficiency when used in the sigma VR, which ensures 90% efficiency for the sigma VR. The small-signal model of the sigma VR is studied to achieve adaptive voltage positioning (AVP). The sigma power architecture can also be applied to low-power point of load (POL) applications to reduce the magnetic component size and improve the efficiency. Finally, the two-stage VR and the sigma VR are briefly compared. / Ph. D.

Pulse power system is widely used for medical, industrial and military applications. The operational principle of the pulse power system is that the energy from the input source is stored in the capacitor bank or superconducting inductive device through a dc-dc converter. Then, when a discharging signal exists, the stored energy is released to the load through pulse forming network (PFN) generating high peak power pulse up to gigawatts within several tens of or hundreds of microseconds. The pulse power system has been originally developed for the defense application. After the format of the voltage compression and voltage addition stages for the short-pulse high power acceleration has been established, it has been evolved to be common. Then, its application has been extended to food processing, medical equipment sterilization and wastewater treatment since many present environmental problems have been known in the early 70's or even earlier. In addition, the pulse power system is newly spotlighted due to the recent world events. The application examples are to treat anthrax-contaminated mail, and the use of accelerators to produce high power X-rays for security screening. Furthermore, the pulse power system has been applied for the tactical weapon system such as electrothermal-chemical (ETC) gun, coilgun and active armor system. Because the pulse power system applied for the tactical weapon system has the potential to be integrated in the military vehicle, a compact, lightweight pulse power system is strongly required for the future weapon system. In this thesis, a distributed power system (DPS) for the capacitor charger is introduced for the application of the active armor system. Furthermore, a design methodology is presented for the front-end converter to achieve the high efficiency as well as the high power density. Design parameters are identified and their impact on the design result is studied. the optimal operating point is determined based on the loss comparison between different operating points. In order to further improve the power density utilizing the unique operation mode i.e. pulse power operation, transformer design using amorphous-based core is provided and the design result is compared with that using ferrite-based core. A 5 kW prototype converter is built up and the experimentation is performed to verify the design. / Master of Science

The growing demand for high voltage, compact pulsed power supplies has gained great attention. It requires power supplies with high power density, low profile and high efficiency. In this thesis, topologies and techniques are investigated to meet and exceed these challenges. Non-isolation type topologies have been used for this application. Due to the high voltage stress of the output, non-isolation topologies will suffer severe loss problems. Extremely low switching frequency will lead to massive magnetic volume. For non-isolation topologies, PWM converters can achieve soft switching to increase switching frequency. However, for this application, due to the large voltage regulation range and high voltage transformer nonidealities, it is difficult to optimize PWM converters. Secondary diode reverse recovery is another significant issue for PWM techniques. Resonant converters can achieve ZCS or ZVS and result in very low switching loss, thus enabling power supplies to operate at high switching frequency. Furthermore, the PRC and LCC resonant converter can fully absorb the leakage inductance and parasitic capacitance. With a capacitive output filter, the secondary diode will achieve natural turn-off and overcome reverse recovery problems. With a three-level structure, low voltage MOSFETs can be applied for this application. Switching frequency is increased to 200 kHz. In this paper, the power factor concept for resonant converters is proposed and analyzed. Based on this concept, a new methodology to measure the performance of resonant converters is presented. The optimal design guideline is provided. A novel constant power factor control is proposed and studied. Based on this control scheme, the performance of the resonant converter will be improved significantly. Design trade-offs are analyzed and studied. The optimal design aiming to increase the power density is investigated. The parallel resonant converter is proven to be the optimum topology for this application. The power density of 31 W/inch3 can be achieved by using the PRC topology with the constant power factor control. / Master of Science