Pre-Charge Half Buffers (PCHB) and NULL convention Logic (NCL) are two major commercially successful Quasi-Delay Insensitive (QDI) asynchronous paradigms, which are known for their low-power performance and inherent robustness. In industry, QDI circuits are synthesized from their synchronous counterparts using custom synthesis tools. Validation of the synthesized QDI implementation is a critical design prerequisite before fabrication. At present, validation schemes are mostly extensive simulation based that are good enough to detect shallow bugs, but may fail to detect corner-case bugs. Hence, development of formal verification methods for QDI circuits have been long desired. The very few formal verification methods that exist in the related field have major limiting factors. This dissertation presents different formal verification methodologies applicable to PCHB and NCL circuits, and aims at addressing the limitations of previous verification approaches. The developed methodologies can guarantee both safety (full functional correctness) and liveness (absence of deadlock), and are demonstrated using several increasingly larger sequential and combinational PCHB and NCL circuits, along with various ISCAS benchmarks. / National Science Foundation (Grant No. CCF-1717420)

This paper addresses the necessity of a correct hydraulic accumulator pre-charge pressure for the optimum performance and in some cases even the essential function of the corresponding hydraulic application. In this context HYDAC has developed a smart product for predictive monitoring of the pre-charge pressure without any need to do a measurement on the gas side of the accumulator – the p0-Guard. The paper gives an overview on the conventional way of checking the pre-charge pressure, the function of the monitoring device and points out the benefits of a predictive monitoring of the accumulator precharge pressure. The benefits are clearly depicted by an analytical view as well as on practical example.

The swift shift of the automotive industry towards electrification is primarily propelled by technological advancements in battery technology. To stay competitive and meet the new demands of the industry, there is a crucial need for novel ideas and innovation. Higher energy density and lower cost makes Battery Electric Vehicles (BEV) competitive and affordable for a wider range of customers. Component space requirements inside a BEV as well as the growing trend towards increasing the voltage of the system from 400 V to 800 V poses new challenges that has to be overcome. Mechanical contactors have the advantage of being simple and easy to use, with low conductive losses. However, they have some drawbacks, such as poor performance when switching under load, limitedability to interrupt fault currents and large controlpower usage. To address these issues, a bidirectional MOSFET configuration can be used to replace the current system. This configuration provides enhanced abilities to quickly suppress fault current, improve robustness, eliminate mechanical failure points, and perform pre-charge sequences without the need for a dedicated branch. Additionally, this configuration maintains current performance in a smaller volume. Within the Battery distribution unit (BDU), this configuration replaces several components, such as thermal fuses, HV contactors, pre-charge relays,pre-charge resistors, and breaker/pyro-fuses with high voltage solid-state components. This study aims to propose potential mitigation methods through a combination of literature survey and comprehensive analysis using Simscape/-MATLAB Simulink models of a fully operational BDU utilizing readily available market components for a 1.2 kV system. The developed model illustrates the thermaland electrical performance of solid-state components in diverse testing scenarios, while maintaining their expected lifecycle. Additionally, sensitivity analysis is conducted using the proposed model to identify themost crucial design parameters within the system. The resulting system performs satisfactory during normal operations, albeit with ten times higher conductive losses attributed to the elevated junction resistance when compared to contactors.Consequently, additional cooling measures are required during harsh operations and DC fast charge. However, the required magnitization energy for a contactor does over time equate or even surpass the MOSFETs conductive losses. The design has established the feasibility of leveraging the primary switchfor pre-charge sequence execution, thus eliminating the need for a dedicated pre-charge branch. The system exhibits strong potential for interrupting both resistive and direct shorts at various locations in the model. However, the low system inductance and the need to avoid introducing any additional inductance into the system renders fault scenarios heavily dependent on said parameter. In conclusion, the proposed model exhibits considerable potential to eliminate numerous auxiliary components therefore reducing losses and offer a more adaptable and consolidated solution. Resulting in a smaller physical footprint and more favorable positioning within the BDU. Moreover, the financial analysis of the system highlights promising prospects for its integration into the drivetrain with the growingmarket trends.

A 2TnC ferroelectric memory gain cell consisting of two transistors and two or more ferroelectric capacitors (FeCAP) is proposed. While a pre-charge transistor allows to access the single cell in an array, the read transistor amplifies the small read signals from small-scaled FeCAPs that can be operated either in FeRAM mode by sensing the polarization reversal current, or in ferroelectric tunnel junction (FTJ) mode by sensing the polarization dependent leakage current. The simultaneous read or write operation of multiple FeCAPs is used to realize compute-in-memory (CiM) algorithms that enable processing of data being represented by both, non-volatilely internally stored data and externally applied data. The internal gain of the cell mitigates the need for 3D integration of the FeCAPs, thus making the concept very attractive especially for embedded memories. Here we discuss design constraints of the 2TnC cell and present the proof-of-concept for realizing versatile (CiM) approaches by means of electrical characterization results.