Microfluidic flow devices coupled with quantitative Raman spectroscopy are able to provide a deep insight into the reaction mechanism and kinetics of electrocatalytic reactions. With a microfluidic flow device made with glass microscope slides and polymer building blocks, the feasibility of this technique was examined by methanol electrooxidation reaction with a Pt working electrode. Pre-calibration of the Raman peak area was done with solutions of known concentrations of methanol and its major oxidation product, i.e., formate, which enabled the time-dependent Raman spectra taken during the reaction to be converted to time-dependent concentrations. These were interpreted in terms of a model with one-dimensional convection and the reaction kinetics. An improved version of this technique was then applied to a comparative study of different alcohols with Ni-based electrodes. This showed the production of formate as the major product from the oxidation of alcohols with vicinal OH groups, leading to the discovery that C-C bond dissociation is a major reaction pathway for vicinal diols and triols if Ni electrocatalysts are used. It is also suggested that the cleavage of C-C bonds is the rate-determining step. The potential use of printed circuit boards (PCB) in the next generation of a novel microfluidic device was explored, as PCB have advantages over regular electrochemical microfluidic substrates, such as simpler electrode fabrication strategies, more wiring layers, and customization of size and shape of electrodes. Pretreatments and electrodeposition protocols of nickel, silver, palladium and platinum on PCB were successfully developed, together with four types of PCB-based microfluidic devices designed with an open-source PCB design software. This work establishes a new electrochemical microfluidic platform for online and in-situ monitoring of electrocatalytic reactions, which can quickly determine the reaction mechanism and kinetics. / Graduate

Neste trabalho foram estudadas as etapas de processo envolvidas na tecnologia Pin-in-Paste (PIP) de soldagem por refusão de componentes convencionais (THCs - Through Hole Components ou Componentes de Furo Passante) em placas de circuito impresso (PCIs), utilizando pasta de solda sem chumbo (lead-free) com liga SAC (Sn-Ag-Cu) de forma a atender as novas exigências ambientais para a montagem eletrônica. Inicialmente foi feito o projeto da PCI de teste com três diferentes componentes THCs e três componentes SMD com encapsulamentos distintos, com o objetivo de reproduzir uma PCI comercial. Foram gerados dois diâmetros de furos diferentes para inserir os THCs, possibilitando o estudo da variação de preenchimento com solda no PTH. Foi proposta uma equação para o cálculo do volume de pasta de solda a ser impresso sobre os furos no processo de montagem. A partir desta equação foram calculadas as dimensões dos furos do estêncil para a PCI de teste. Os parâmetros de impressão foram otimizados em função da variação de pressão e da velocidade do rodo. Duas curvas de refusão foram utilizadas, uma convencional e outra otimizada para verificar a variação na geração de defeitos. A impressão de pasta de solda ficou superior ao projetado, o que resultou em todas as amostras terem solda acima do parâmetro mínimo de aceitabilidade de volume de 75% de preenchimento do PTH. Esta sobre impressão ocasionou defeitos em boa parte dos componentes, excesso de solda nos filetes e resíduos de fluxo na solda nos PTHs. Tais defeitos foram expressivos para todos os THCs, mostrando que o excesso de pasta impressa foi decisivo na geração de defeitos para todas as combinações das variáveis estudadas. Os SMDs tiveram solda aceitável, apresentando apenas alguns casos de excesso de fluxo ou pouca solda em alguns QFPs devido ao uso de ilhas com dimensões maiores que o exigido em norma. O processo de Pin In Paste se mostra viável como substituto da solda onda em linhas de montagem para placas com SMDs e THCs, mas estudos posteriores deverão ser realizados para a geração de um modelo confiável de projeto de PCIs e estêncil com solda lead-free para que tal processo seja utilizado em grande escala na indústria. / This study describes the process steps involved in Pin-in-Paste (PIP) reflow soldering technology in printed circuit boards (PCBs) using lead-free solder paste with SAC alloy (Sn-Ag-Cu) in order to attend new environmental requirements for the electronics assembly. Initially it was designed a PCB test with three different THCs (Through Hole Component) and three different SMD (Surface Mount Device) packages in order to reproduce a commercial board. It was generated two different diameters of holes to insert the THCs, aiming to study the solder fill variation in PTH. An equation was proposed for calculating the volume of solder paste to be printed over the holes in the assembly process. From this equation it was calculated the dimensions of the holes of the stencil. The printing parameters were optimized according to the variation of pressure and speed of the squeegee. Two reflow curves were used in the process, a conventional one and an optimized one to determine the variations in the generation of soldering defects. The printed solder paste volume was higher than projected, which resulted in solder excess, causing defects in most of the components, such as excess solder in the fillet and solder flux residues in PTHs. Such defects were significant for all THCs, showing that the excess paste that was printed caused critical defects for all combinations of variables. Regarding that all samples were above the reflow minimum acceptable volume of 75% coverage of PTH. The SMDs solders were acceptable, with only few cases of solder flux excess. The Pin in Paste process was observed as a good option to replace the wave soldering thermal process for mixed PCBs. Further studies should be conducted to generate a reliable model of PCB and stencil design.

In this thesis, vibration induced fatigue life analysis of axial leaded Tantalum &amp / Aluminum capacitors, PDIP and SM capacitors mounted on the printed circuit boards are performed. This approach requires the finite element model, material properties and dynamic characteristics of the PCB. The young modulus of the PCB material is obtained from 3 point bending tests, resonance frequencies are obtained from modal tests and transmissibility&amp / #8217 / s of the PCB are obtained from transmissibility tests which are used as fatigue analysis inputs. Step Stress Tests are performed to obtain failure times of the tested electronic components which are also used as the numerical fatigue analysis inputs. Consecutively, fatigue analysis of a sample PCB used in military systems is aimed since it is important to compare the calculated fatigue damage to estimated life limits in order to determine which component(s), if necessary, must be moved to positions of lower damage . For this purpose, power PCB of the power distribution unit used in Leopard 1 battle tank is examined. Numerical fatigue analysis coupled with accelerated life test whose profile is convenient to military platforms is performed. Furthermore, the effects of eccobond and silicone on the fatigue life of the components are also surveyed since these techniques are common in electronic packaging. In addition, mean-time-to-failure values are obtained for the tested components by using Weibull distribution. Finally, sensitivity analysis is performed to indicate the effect of certain parameters on the fatigue life of a sample axial leaded capacitor.

The ever-increasing need for higher bandwidth and density is one of the motivations for extensive research on planar optoelectronic structures on printed circuit board (PCB) substrates. Among these applications, optical interconnects have received considerable attention in the last decade. Several optical interconnect techniques, such as free space, guided wave, board level and fiber array interconnects, have been introduced for system level applications. In all planar optoelectronic systems, optical waveguides are crucial elements that facilitate signal routing. Low propagation loss, high reliability and manufacturability are among the requirements of polymer optical waveguides and polymer passive devices on PCB substrates for practical applications. Besides fabrication requirements, reliable characterization tools are needed to accurately and nondestructively measure important guiding properties, such as waveguide propagation loss. In three-dimensional (3D) fully embedded board-level optical interconnects, another key challenge is to realize efficient optical coupling between in-plane waveguides and out-of-plane laser/detector devices. Driven by these motivations, the research presented in this thesis focuses on some fundamental studies of optical interconnects for PCB substrates, e.g., developing low-loss optical polymer waveguides with integrated efficient out-of-plane couplers for optical interconnects on printed circuit board substrates, as well as the demonstration of a novel free-space optical interconnect system by using a volume holographic thin film. Firstly, the theoretical and experimental investigations on the limitations of using mercury i-line ultraviolet (UV) proximity photolithography have been carried out, and the metallization techniques for fine copper line formation are explored. Then, a new type of low-loss polymer waveguides (i.e., capped waveguide) is demonstrated by using contact photolithography with considerable performance improvement over the conventional waveguides. To characterize the propagation properties of planar optical waveguides, a reliable, nondestructive, and real-time technique is presented based on accurately imaging the scattered light from the waveguide using a sensitive charge coupled device (CCD) camera that has a built-in integration functionality. To provide surface normal light coupling between waveguides and optoelectronic devices for optical interconnects, a simple method is presented here to integrate 45° total internal reflection micro-mirrors with polymer optical waveguides by an improved tilted beam photolithography (with the aid of de-ionized water) on PCBs. A new technique is developed for a thin layer of metal coating on the micro-mirrors to achieve higher reflection and coupling efficiency (i.e., above 90%). The combination of the capped waveguide technique and the improved tilted UV exposure technique along with a hard reusable metal mask for metal deposition eliminates the usage of the traditional lift-off process, greatly simplifies the process, and reduces fabrication cost without sacrificing the coating quality. For the study of free-space optical interconnects, a simple system is presented by employing a single thin-film polymeric volume holographic element. One 2-spherical-beam hologram is used to link each point light source with the corresponding photodetector. An 8-channel free-space optical interconnect system with high link efficiency is demonstrated by using a single volume holographic element where 8 holograms are recorded.

Neste trabalho foram estudadas as etapas de processo envolvidas na tecnologia Pin-in-Paste (PIP) de soldagem por refusão de componentes convencionais (THCs - Through Hole Components ou Componentes de Furo Passante) em placas de circuito impresso (PCIs), utilizando pasta de solda sem chumbo (lead-free) com liga SAC (Sn-Ag-Cu) de forma a atender as novas exigências ambientais para a montagem eletrônica. Inicialmente foi feito o projeto da PCI de teste com três diferentes componentes THCs e três componentes SMD com encapsulamentos distintos, com o objetivo de reproduzir uma PCI comercial. Foram gerados dois diâmetros de furos diferentes para inserir os THCs, possibilitando o estudo da variação de preenchimento com solda no PTH. Foi proposta uma equação para o cálculo do volume de pasta de solda a ser impresso sobre os furos no processo de montagem. A partir desta equação foram calculadas as dimensões dos furos do estêncil para a PCI de teste. Os parâmetros de impressão foram otimizados em função da variação de pressão e da velocidade do rodo. Duas curvas de refusão foram utilizadas, uma convencional e outra otimizada para verificar a variação na geração de defeitos. A impressão de pasta de solda ficou superior ao projetado, o que resultou em todas as amostras terem solda acima do parâmetro mínimo de aceitabilidade de volume de 75% de preenchimento do PTH. Esta sobre impressão ocasionou defeitos em boa parte dos componentes, excesso de solda nos filetes e resíduos de fluxo na solda nos PTHs. Tais defeitos foram expressivos para todos os THCs, mostrando que o excesso de pasta impressa foi decisivo na geração de defeitos para todas as combinações das variáveis estudadas. Os SMDs tiveram solda aceitável, apresentando apenas alguns casos de excesso de fluxo ou pouca solda em alguns QFPs devido ao uso de ilhas com dimensões maiores que o exigido em norma. O processo de Pin In Paste se mostra viável como substituto da solda onda em linhas de montagem para placas com SMDs e THCs, mas estudos posteriores deverão ser realizados para a geração de um modelo confiável de projeto de PCIs e estêncil com solda lead-free para que tal processo seja utilizado em grande escala na indústria. / This study describes the process steps involved in Pin-in-Paste (PIP) reflow soldering technology in printed circuit boards (PCBs) using lead-free solder paste with SAC alloy (Sn-Ag-Cu) in order to attend new environmental requirements for the electronics assembly. Initially it was designed a PCB test with three different THCs (Through Hole Component) and three different SMD (Surface Mount Device) packages in order to reproduce a commercial board. It was generated two different diameters of holes to insert the THCs, aiming to study the solder fill variation in PTH. An equation was proposed for calculating the volume of solder paste to be printed over the holes in the assembly process. From this equation it was calculated the dimensions of the holes of the stencil. The printing parameters were optimized according to the variation of pressure and speed of the squeegee. Two reflow curves were used in the process, a conventional one and an optimized one to determine the variations in the generation of soldering defects. The printed solder paste volume was higher than projected, which resulted in solder excess, causing defects in most of the components, such as excess solder in the fillet and solder flux residues in PTHs. Such defects were significant for all THCs, showing that the excess paste that was printed caused critical defects for all combinations of variables. Regarding that all samples were above the reflow minimum acceptable volume of 75% coverage of PTH. The SMDs solders were acceptable, with only few cases of solder flux excess. The Pin in Paste process was observed as a good option to replace the wave soldering thermal process for mixed PCBs. Further studies should be conducted to generate a reliable model of PCB and stencil design.

M. Tech. (Department of Metallurgical Engineering, Faculty of Engineering and Technology), Vaal University of Technology. / Dust generated during comminution of end of life printed circuit boards (PCB), typically having d80 of 212 μm, contains copper and gold up to 6.32 % and 635 g/ton, respectively. The dust particles being highly diverse in material makeup, an hydrometallurgical processing scheme able to selectively recover target values was studied. Use of mineral acids will result in multiple metal dissolution which will complicate subsequent solution treatments. Detailed characterization of the dust was first carried out, and leaching scheme were thereafter investigated to selectively recover gold and copper from the dust, in three leaching stages. Different conditions of ammonia and thiourea leaching were investigated to optimize agitation speed, reagents concentration, temperature and leaching time. The leaching kinetics of these elements from the dust under different prevailing leaching conditions were studied. Elemental composition of the dust size fractions indicates metal contents generally increase with decreasing dust particle size, down to – 53 μm size, which contains up to 635 g/ton Au, 25.43 % Fe, and 1.40 % Cu, compared to 51 g/ton Au, 3.07 % Fe and 6.32 % Cu in the 150–212 μm fraction. Thermodynamically, under oxidative ammonia leaching, zinc and copper ammine complex is feasible, yet zinc recovery is low. For 75 – 106 μm dust size, 2 M NH4OH, 17.5 M H2O2, 1 atm. pressure and 400 rpm in Parr reactor, Cu and Zn recoveries were 92 % and 50 %, while the activation energies evaluated within 283 – 313 K gave 47.39 kJ/mol and 33.12 kJ/mol. The kinetic analysis for copper leaching gave best correlation coefficient (R2) of 0.9804 when fitted into the chemical control model, and the rate constant was 4.4 x 10-3 at 313 K. The presence of base metals frustrates direct gold recovery from the dust using thiourea with sulphuric acid and hydrogen peroxide. Therefore, the residue obtained from the first stage copper leach was acid washed to remove iron and other residual base metal contents with 5 M H2SO4, at 333 K, 400 rpm for 2 hours. Recovery analysis shows that about 75-98 % Fe, 54-65 % Zn and 96-98 % Ni were recovered under this condition while Cu was less than 7 % at all PSDs; copper having been selectively removed at the first stage. Using 75 – 106 μm dust fraction, gold recovery was optimum when the acid wash residue was leached with 0.5 M thiourea (SC(NH2)2), 0.5 M sulphuric acid (H2SO4), 0.1 M hydrogen peroxide (H2O2) under 1 atm. pressure, 298 K and 400 rpm for 4 hours. The recovery was 98 % Au. Using this optimum for other size fractions, over 98 % gold was recovered from 150–212 μm, 106 – 150 μm and 75 – 106 μm dust while 71 % and 68 % Au were recovered from 53 – 75 μm and – 53 μm respectively. The lower recovery at the finest sizes can be due to the quantity of the gold contents deported in this particle size, which will require higher reagent dosage. The kinetic analysis gave best correlation coefficient (R2) of 0.99 when fitted to the chemical control leaching model. From this data, a process flowsheet was proposed to give separate streams rich in copper and gold values from the processed dust, with detailed processing parameters. This is considered a readily scalable process solution for retrieving gold and copper from PCB dust.

[pt] O crescimento da produção de resíduos sólidos devido a evolução tecnológica, principalmente nos países em desenvolvimento, vem apresentando-se de maneira acelerada. Esta evolução acarreta na produção de novos produtos eletrônicos mais atualizados e, cada vez mais sofisticados quanto à composição química, com novas funcionalidades, tornando os antigos dispositivos obsoletos. O consumo exarcebado destes novos produtos contribui para um problema que ganha cada vez mais relevância no cenário mundial, o acúmulo de lixo eletrônico de origem urbana. O presente estudo contemplará como matéria prima amostras de placas de circuito impresso de computadores, conhecidas como PCIs, que são um padrão de barramentos, destinado a conectar periféricos à placa-mãe. Tendo em vista que nestes resíduos os teores de metais são tipicamente superiores àqueles de reservas naturais, torna-se interessante buscar rotas que viabilizem a reciclagem desses resíduos com a concomitante recuperação de constituintes de interesse ou concentração de precursores em distintos grupos para a posterior recuperação de metais. Nesta abordagem, foram realizadas análises termogravimétricas para acompanhar as melhores condições de processo e caracterização do material e produtos através de MEV/EDS. Assim, este material, tipicamente constituído por material orgânico (ex: plásticos como PVC) e constituintes inorgânicos (ex: metais e ligas metálicas), será submetido a um processamento térmico em forno tubular a 350 graus C em atmosfera inerte, seguido de etapas de concentração. A partir de 300 graus C a perda de massa se mantém constante, em torno de 30 por cento, e nas seguintes etapas aplicadas, 15 por cento da amostra total em constituintes metálicos com alto valor agregado, no caso Cu, Ni e Au, podem seguir para recuperação. / [en] The production of solid residues due to technological development has been increasing fast, mainly in developing countries. This growth leads to the manufacture of improved electronic products with varied functions, which not only are better versions of the old ones but also more sophisticated in their chemical compounds. The excessive consumption of the new devices contributes to an issue which has been increasing internationally: the accumulation of electronic waste. The raw material used in this study are samples of computer printed circuit boards (PCBs), which are a bus pattern that connects peripherals to the motherboard. Since the metal content in these residues are typically more elevated than in the ones located in natural reserves, it is interesting to find ways to recycle those residues while recovering components of interest or precursor concentrations in distinct groups for later metal recovery. Thermogravimetric analysis were performed on this approach in order to observe the best conditions of the process and the characterization of material and products was through SEM/EDS. Thus, this material, typically composed by organic material (such as plastic or PVC) and inorganic constituents (such as metals and alloys), undergoes a thermal processing in tubular furnace at 350 C degrees in inert atmosphere, followed by the concentration steps. The mass loss is constant from 300 C degrees on, around 30 percent. In the following steps, 15 percent of the total sample presents metallic components with high added value, such as Cu, Ni and Au, may be recovered.

<p dir="ltr">Portable sensing enables an enhanced form of disease monitoring due to its accessible form-factors, low costs, and insights into user health, along with enhanced detection methods due to its many use cases for at-home or in-field applications. To that end, electrochemistry has been a widely used technique in characterization, detection, and diagnostics. Electrochemical Impedance Spectroscopy (EIS) is an electrochemical technique that enables electrode surface characterization through changes in impedance across a given frequency range making it sensitive to interactions at the electrode surface and enabling the detection and quantification of analytes. While EIS has been traditionally limited to benchtop potentiostats, advancements in integrated circuits (ICs) have since enabled the miniaturization of potentiostats for at-home or field applications. However, implementation of EIS in a portable format is still limited by discontinuous measurements, high cost, or designs not fit for portability. This work revolves around the development of a miniaturized potentiostat that can implement EIS to better accommodate the need for miniaturized sensing platforms. My design uses the AD5941 IC which is a single-chip potentiostat analog-front-end enabling a small form-factor that fits in the palm of the user’s hand. The device was able to characterize a resistor-capacitor circuit with errors as low as 0.33% and quantify the concentration of a redox active compound with a 6.2% error, providing agreeable results with a commercial benchtop potentiostat and demonstrating our device’s potential for diagnostic applications. Our working frequency range of 200 kHz – 0.15 Hz, coupled with high system configurability and a cost of $50 makes our device an accessible option for at-home and portable applications. Future work to implement truly wireless functionalities, such as WiFi or Bluetooth Low Energy, along with experimental testing of biological substances will create a truly robust platform for portable diagnostic and sensing applications.</p>

<p>Flexible printed circuit boards (flex PCBs) are used in a wide range of electronic devices today due to their light weight, bendability, extensive wiring possibilities, and low-cost manufacturing techniques. The general trend in the flex PCB industry is further miniaturization alongside increasing functionality per device and reduced costs. To meet these demands, a new generation of low cost manufacturing technologies is being developed to enable structures with smaller lateral dimensions and higher packing densities.</p><p>Wet etching is today the most cost-efficient method for producing a large number of through-foil structures in flex PCBs. However, conventional wet etch techniques do not allow for through-foil structures with aspect ratios over 1 – a fact that either necessitates thin and mechanically weak foils or puts severe limitations on the packing density. The fabrication techniques presented in this thesis allow for through-foil structures with higher aspect ratios and packing densities using wet etching. To achieve high aspect ratios with wet etching, the flex PCB foils are pre-treated with irradiation by swift heavy ions. Each ion that passes through the foil leaves a track of damaged material which can be subsequently etched to form highly vertical pores. By using conventional flex PCB process techniques on the porous foils, high aspect ratio metallized through-foil structures are demonstrated.</p><p>The resulting structures consist of multiple sub-micrometer sized wires. These structures are superior to their conventional counterparts when it comes to their higher aspect ratios, higher possible packing densities and low metallic cross-section. Furthermore, metallized through-foil structures with larger areas and more complicated geometries are possible without losing the mechanical stability of the foil. This in turn enables applications that are not possible using conventional techniques and structures. In this thesis, two such applications are demonstrated: flex PCB vertical thermopile sensors and substrate integrated waveguides for use in millimeter wave applications.</p>

Flexible printed circuit boards (flex PCBs) are used in a wide range of electronic devices today due to their light weight, bendability, extensive wiring possibilities, and low-cost manufacturing techniques. The general trend in the flex PCB industry is further miniaturization alongside increasing functionality per device and reduced costs. To meet these demands, a new generation of low cost manufacturing technologies is being developed to enable structures with smaller lateral dimensions and higher packing densities. Wet etching is today the most cost-efficient method for producing a large number of through-foil structures in flex PCBs. However, conventional wet etch techniques do not allow for through-foil structures with aspect ratios over 1 – a fact that either necessitates thin and mechanically weak foils or puts severe limitations on the packing density. The fabrication techniques presented in this thesis allow for through-foil structures with higher aspect ratios and packing densities using wet etching. To achieve high aspect ratios with wet etching, the flex PCB foils are pre-treated with irradiation by swift heavy ions. Each ion that passes through the foil leaves a track of damaged material which can be subsequently etched to form highly vertical pores. By using conventional flex PCB process techniques on the porous foils, high aspect ratio metallized through-foil structures are demonstrated. The resulting structures consist of multiple sub-micrometer sized wires. These structures are superior to their conventional counterparts when it comes to their higher aspect ratios, higher possible packing densities and low metallic cross-section. Furthermore, metallized through-foil structures with larger areas and more complicated geometries are possible without losing the mechanical stability of the foil. This in turn enables applications that are not possible using conventional techniques and structures. In this thesis, two such applications are demonstrated: flex PCB vertical thermopile sensors and substrate integrated waveguides for use in millimeter wave applications. / wisenet