This master thesis describes the design of increasing the efficiency of production lines with solder robots. In beginning of this work is a description of product and current process. There are also variants of design solutions for soldering palettes and the best on is chosen. The last part of this work includes design automation soldering process.

Trend towards downsizing the product size and at the same time to bring more functionality in electronic products, demands electrically interconnecting several miniaturized electronic components with high counts of I\Os (Input/Out put) on smaller and smaller size printed wiring boards [PWB]. These miniature components occupy lower foot print area but require higher routing interconnection densities. However, the conventional multilayer board technologies exhibit limitations when there is need to connect very high I\O components such as ball grid arrays, which require blind and buried interconnections within the multilayer mono-block. This limitation has given raise to newer methods of multi layer construction. Build–up multilayer PWB is now the technology of choice for enhanced routing capability including blind and buried interlayer connections. Build up methods are based on making very small vias within dielectric layers followed by metalisation. Typically blind and buried vias are very small, and hence called “micro vias” connecting the layers selectively within the multilayer mono-block. Buried vias make the interconnection between the consecutive layers, and blind vias connect the surface layers to any one of the interior layers in the build up multilayer board. If the blind vias are filled with a dielectric, the entire top and bottom surface area becomes available for high -density component mounting. The crux in build up board technologies is the method of creating micro-holes; a micro hole is a hole, which is less than 150 micro meter in diameter. Efforts are made to replace existing metalising techniques with “paste filling” methodologies, which would result in “SOLID CONDUCTING VIAS” CALLED AS “MICRO -INTERCONNECTS” The work reported in this thesis aims at demonstrating one such innovative ‘solid conducting via’ formation without using any of the known micro-hole formation techniques. Based on the results obtained some useful conclusions have been drawn which will perhaps go a long way in the name of “PRINTED PILLAR TECHNOLOGY” a novel methodology for building multilayer suitable for very high I\O components such as “ball grid arrays.”

Considering the rapid increase in the ICT (Information & Communication Technology) products in use, there is a risk of an increase in GHG emissions and electronic waste accumulation in the ICT sector. Therefore, it becomes important to account for the emissions in the ICT sector in order to take steps to mitigate them. There are several methods put forward under ETSI, ITU-T, GHG protocol, etc., which can be used to measure the emissions in the ICT sector. Two such methods are Product Life Cycle Assessment (PLCA) and Spend-based, which are used in this study to account for scope 3, category 1 emissions in the ICT sector. Scope 3, category 1 emissions are released during the raw material acquisition and part production phase of the ICT product’s life cycle and account for a major portion of the overall emissions. As the ICT sector is a very huge field of study in itself, two ICT products, namely smartphones and laptops, are considered in this study to calculate their overall scope 3, category 1 emissions. A list of influential components in smartphones and laptops is defined to be included in the Excel Management Life Cycle Assessment (EMLCA) tool to calculate the scope 3, category 1 emissions. A comprehensive comparison between PLCA and Spend-based methods is also studied during the process of calculating their emissions. These observations are then used to make critical analyses and compare the two methods under results and discussions based on various parameters described under them. Both the methods were found to be suitable for calculating the emissions, with some uncertainty, although the Spend-based method was a quicker approach to do so. The PLCA method, although more complex, was found to be more suitable for ICT product eco-design. Both methods required a different set of primary data and were sensitive to various components in smartphones and laptops. This study illustrates the parameters that affect PLCA and Spend-based methods and discusses the pros and cons of them depending on the situations they are used in.

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / Eutectic (63% tin-37% lead) or near-eutectic (40% tin-60% lead) tin-lead solder is widely used for creating electrical interconnections between the printed wiring board (PWB) and the components mounted on the board surface. For components mounted directly on the PWB mounting pads, that is, surface mounted components, the tin-lead solder also constitutes the mechanical interconnection. Eutectic solder has a melting point of 183°C (361°F). It is important to realize that its homologous temperature, defined as the temperature in degrees Kelvin over its melting point temperature (T(m)), also in degrees Kelvin, is defined as T/T(m). At room temperature (25°C = 298K), eutectic solder's homologous temperature is 0.65. It is widely acknowledged that materials having a homologous temperature ≥ 0.5 are readily subject to creep, and the solder joints of printed wiring assemblies are routinely exposed to temperatures above room temperature. Hence, solder joints tend to be subject to both thermal fatigue and creep. This can lead to premature failures during service conditions. The geometry, that is, the lead configuration, of the joints can also affect failure. Various geometries are better suited to withstand failure than others. The purpose of this paper is to explore solder joint failures of dual in-line (DIP) integrated circuit components, leadless ceramic chip carriers (LCCCs), and gull wing and J-lead surface mount components mounted on PWBs.