Thesis (M.S.)--University of North Texas, May, 2008. / Title from title page display. Includes bibliographical references.

Soft processors simplify hardware design by being able to implement complex control strategies using software. However, they are not fast enough for many intensive data-processing tasks, such as highly data-parallel embedded applications. This thesis suggests adding a vector processing core to the soft processor as a general-purpose accelerator for these types of applications. The approach has the benefits of a purely software-oriented development model, a fixed ISA allowing parallel software and hardware development, a single accelerator that can accelerate multiple functions in an application, and scalable performance with a single source code. With no hardware design experience needed, a software programmer can make area-versus-performance tradeoffs by scaling the number of functional units and register file bandwidth with a single parameter. The soft vector processor can be further customized by a number of secondary parameters to add and remove features for the specific application to optimize resource utilization. This thesis shows that a vector processing architecture maps efficiently into an FPGA and provides a scalable amount of performance for a reasonable amount of area. Configurations of the soft vector processor with different performance levels are estimated to achieve speedups of 2-24x for 5-26x the area of a Nios II/s processor on three benchmark kernels. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

As we continue to be able to put an increasing number of transistors on a single chip, the answer to the perpetual question of what the best processor we could build with the transistors is remains uncertain. Past work has shown that heterogeneous multiprocessor systems provide benefits in performance and efficiency. This thesis explores heterogeneous systems composed of a traditional sequential processor (CPU) and highly parallel graphics processors (GPU). This thesis presents a tightly-coupled heterogeneous chip multiprocessor architecture for general-purpose non-graphics computation and a limit study exploring the potential benefits of GPU-like cores for accelerating a set of general-purpose workloads. Pangaea is a heterogeneous CMP design for non-rendering workloads that integrates IA32 CPU cores with GMA X4500 GPU cores. Pangaea introduces a resource partitioning of the GPU, where 3D graphics-specific hardware is removed to reduce area or add more processing cores, and a 3-instruction extension to the IA32 ISA that supports fast communication between CPU and GPU by building user-level interrupts on top of existing cache coherency mechanisms. By removing graphics-specific hardware on a 65 nm process, the area saved is equivalent to 9 GPU cores, while the power saved is equivalent to 5 cores. Our FPGA prototype shows thread spawn latency improvements from thousands of clock cycles to 26. A set of non-graphics workloads demonstrate speedups of up to 8.8x. This thesis also presents a limit study, where we measure the limit of algorithm parallelism in the context of a heterogeneous system that can be usefully extracted from a set of general-purpose applications. We measure sensitivity to the sequential performance (register read-after-write latency) of the low-cost parallel cores, and latency and bandwidth of the communication channel between the two cores. Using these measurements, we propose system characteristics that maximize area and power efficiencies. As in previous limit studies, we find a high amount of parallelism. We show, however, that the potential speedup on GPU-like systems is low (2.2x - 12.7x) due to poor sequential performance. Communication latency and bandwidth have comparatively small performance effects (<25%). Optimal area efficiency requires a lower-cost parallel processor while optimal power efficiency requires a higher-performance parallel processor than today's GPUs. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

Hydrogen has gained interest as fuel recently as the harmful effects of fossil fuels on the environment can no longer be ignored. Hydrogen, which produces no pollutants, forms the feed for cleaner fuel cells systems currently in use. Fuel cells, although not as economically viable as fossil fuels, have found a foothold in the energy market in various markets like power backup and use in remote locations. Production of hydrogen is still largely done via fossil fuel reforming and this technology has received renewed interest for use with fuel cells in the form of micro- reformers or fuel processors. This study entailed the performance benchmarking of a so called Best-in-Class commercial micro reformer (as available in 2010), the 1 kW WS FLOX Reformer, and was undertaken under the auspices of the national HySA programme. The study’s focus was primarily on reformate output quality (carbon monoxide concentration), and start up time, thermal efficiency and hydrogen output (15 SCLM). The reformer consisted of a combustion section encased in an outer reforming section consisting of three reactors in series, steam reforming, water gas shift and selective methanation. As-provided temperature control is simplified though the use of only one temperature setpoint in the combustion chamber and temperature control in the CO clean up stages obtained through means of heat transfer with incoming water being evaporated. Combustion takes place through flame combustion or by means of the supplier’s patented FLOX (flameless oxidation) combustion. The purchased FLOX Reformer assembly was integrated into a fully automated unit with all balance of plant components as well as microGC and flue gas analysis for measurement of outlet conditions. The FLOX Reformer was tested at multiple combustion temperatures, combustion flowrates, reforming loads and steam-to-carbon ratios to obtain a wide set of benchmark data. From the testing it was found that the reformer was able to produce the necessary 15 SCLM hydrogen with a carbon monoxide purity of less than 10 ppm as required in fuel cells for all testing if the reaction temperatures were within the recommended limits. Intermediary water gas shift analysis showed methane and carbon monoxide conversion in the reforming and water gas shift stages to be identical to thermodynamic equilibrium conversion – 95% and higher for all temperatures. iii Selective methanation conversion obtained was 99%, but not always at equilibrium conversion due to increased selective methanation temperatures, where carbon dioxide methanation was also observed at the higher temperatures. Temperature control through heat exchange with incoming water in the CO removal stages was found to be less than ideal as the temperature inside these stages fluctuated dramatically due to inaccuracies in the water pump and a lagged response to flowrate changes. Startup times of less than an hour was observed for multiple combustion flowrates and the reformer boasts a standby function to reduce this to less than half an hour. The thermal efficiency was independently confirmed and tested and found to be higher than 70 % for flame combustion and on par with other commercially available fuel processors. The suppliers trademark FLOX combustion only reaching 65% due to decreased combustion efficiency.

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Thesis (M.S.)--University of Delaware, 2007. / Principal faculty advisor: Guang R. Gao, Dept. of Electrical and Computer Engineering. Includes bibliographical references.

<p>Future radars require more flexible and faster radar signal processing chain than commercial radars of today. This means that the demands on the processors in a radar signal system, and the desire to be able to compute larger amount of data in lesser time, is constantly increasing. This thesis focuses on commercial micro-processors of today that can be used for Active Electronically Scanned Array Antenna (AESA) based radar, their physical size, power consumption and performance must to be taken into consideration. The evaluation is based on theoretical comparisons among some of the latest processors provided by PACT, PicoChip, Intrinsity, Clearspeed and IBM. The project also includes a benchmark made on PowerPC G5 from IBM, which shows the calculation time for different Fast Fourier Transforms (FFTs). The benchmark on the PowerPC G5 shows that it is up to 5 times faster than its predecessor PowerPC G4 when it comes to calculate FFTs, but it only consumes twice the power. This is due to the fact that PowerPC G5 has a double word length and almost twice the frequency. Even if this seems as a good result, all the PowerPC´s that are needed to reach the performance for an AESA radar chain would consume too much power. The thesis ends up with a discussion about the traditional architectures and the new multi-core architectures. The future belongs with almost certainty to some kind of multicore processor concept, because of its higher performance per watt. But the traditional single core processor is probably the best choice for more moderate-performance systems of today, if you as developer looking for a traditional way of programing processors.</p>

High bandwidth of networks demands high performance communication processors that integrate application processing, network processing, and system support functions into a single, low cost System-On-Chip (SOC) solution. However, conventional processors, when used in network related applications, are beset by the overhead of save/restore of register context, cache misses due to fetching interrupt handler from memory, and the possibility of NIC buffer overflow. Therefore, this paper analyzes the effectiveness of multithreading to service interrupts on an embedded processor from the perspective of a Network processor and a Communication processor. A Simulation environment enhanced with a multithreaded hardware execution model is used and our results reveal that multithreading for interrupts from a single NIC brings a fair improvement in performance of Network processors and little or no effect on Communication processors. However, our analysis also show that multithreading for interrupts has a lot of potential when applied to communication processors with multiple interrupt sources, such as Ethernet, ATM, USB, and HDLC. Index terms: Multithreading, UDP, IP, device driver, interrupt processing, communication processor. / Graduation date: 2003