Spelling suggestions: "subject:"programmable"" "subject:"rogrammable""
41 |
PLC implementation of online, PRBS-based tests for mechanical system parameter estimation.Rampersad, Vaughan. January 2009 (has links)
This thesis investigates the use of correlation techniques to perform system identification tests, with the objective of developing online test methods to perform mechanical parameter extraction as well as machine diagnostics. More specifically, these test methods must be implemented on a Programmable Logic Controller (PLC) in combination with Variable Speed Drives (VSD). Models for motor-based mechanical systems are derived and other documented methods for parameter identification of mechanical systems are discussed. An investigation is undertaken into the principle that the impulse response of a system may be obtained when a test signal with an impulsive autocorrelation is injected into the system. The theory of using correlation functions to determine the numerical impulse response of a system is presented. Suitable test signals, pseudorandom binary sequences (PRBS) are
analysed, and their generation and properties are discussed. Simulations are presented as to how the various properties of the PRBS test signals influence the resulting impulse response curve. Further simulations are presented that demonstrate how PRBS-based tests in conjunction with a curve-fitting method, in this case the method of linear least squares, can provide a fair estimation of the parameters of a mechanical system. The implementation of a correlation based online testing routine on a PLC is presented. Results from these tests are reviewed and discussed. A SCADA system that has been designed is discussed and it is shown how this system allows the user to perform diagnostics on networked drives in a distributed automation system. Identification of other mechanical phenomena such as elasticity and the
non-linearity introduced by the presence of backlash is also investigated. / Thesis (M.Sc.Eng.)-University of KwaZulu-Natal, Durban, 2009.
|
42 |
Alternative techniques for Built-In Self-Test of Field Programmable Gate ArraysNewalkar, Aditya, January 2005 (has links) (PDF)
Thesis(M.S.)--Auburn University, 2005. / Abstract. Vita. Includes bibliographic references.
|
43 |
Variable precision analysis for FPGA synthesis /Chang, Mark L. January 2004 (has links)
Thesis (Ph. D.)--University of Washington, 2004. / Vita. Includes bibliographical references (leaves 95-104).
|
44 |
Partitioning and routing for multi-FPGA systems /Mak, Wai-kei, January 1998 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 1998. / Vita. Includes bibliographical references (leaves 111-116). Available also in a digital version from Dissertation Abstracts.
|
45 |
JPG : a partial bitstream generation tool to support partial reconfiguration in Virtex FPGAs /Raghavan, Anup Kumar. January 2004 (has links) (PDF)
Thesis (M.Eng.Sc.) - University of Queensland, 2002. / Includes bibliography.
|
46 |
Place and route techniques for FPGA architecture advancement /Sharma, Akshay. January 2005 (has links)
Thesis (Ph. D.)--University of Washington, 2005. / Includes bibliographical references (leaves 129-132).
|
47 |
Durcissement de circuits logiques reconfigurables / Hardening basic blocks in a mesh of clusters FPGABen Dhia, Arwa 14 November 2014 (has links)
Avec les réductions d'échelle, les circuits électroniques deviennent de plus en plus petits, plus performants, consommant moins de puissance, mais aussi moins fiables. En effet, la fiabilité s'est récemment érigée en défi majeur dans l'industrie micro-électronique, devenant un critère de conception important, au même titre que la surface, la consommation de puissance et la vitesse. Par exemple, les défauts physiques dus aux imperfections dans le procédé de fabrication ont été observés plus fréquemment, affectant ainsi le rendement des circuits. Par ailleurs, les circuits nano-métriques deviennent pendant leur durée de vie plus vulnérables aux rayonnements ionisants, ce qui cause des fautes transitoires. Les défauts de fabrication, aussi bien que les fautes transitoires, diminuent la fiabilité des circuits intégrés. En avançant dans les nœuds technologiques, les circuits logiques programmables de type FPGA sont les premiers à entrer sur le marché, grâce à leur faible coût de développement et leur flexibilité qui leur permet d'être utilisés pour n'importe quelle application. Les FPGA possèdent des caractéristiques attrayantes, notamment pour les applications spatiales et aéronautiques, où la reconfigurabilité, les hautes performances et la faible consommation de puissance peuvent être exploitées pour développer des systèmes innovants. Néanmoins, les missions ont lieu dans un environnement rude, riche en radiations pouvant produire des erreurs soft dans les circuits électroniques. Ceci montre l'importance de la fiabilité des FPGA en tant que critère de conception dans les applications critiques. La plupart des FPGA commerciaux ont une architecture matricielle et leurs blocs logiques sont regroupés en clusters. Ainsi, cette thèse s'intéresse à la tolérance aux fautes des blocs de base ( blocs logiques élémentaires (BLE) et boîtes d'interconnexion ) dans un FPGA de type « matrice de clusters ». Dans le but d'améliorer la fiabilité de ces blocs, il est impératif de pouvoir d'abord l'évaluer, pour ensuite sélectionner la bonne technique de durcissement selon le budget mis à disposition. C'est bien le plan principal de cette thèse. Elle a essentiellement deux objectifs : (a) analyser la tolérance aux fautes des blocs de base dans un FPGA de type « matrice de clusters », et identifier les composants les plus vulnérables. (b) proposer des méthodes de durcissement à différents niveaux de granularité, en fonction du budget de durcissement. En ce qui concerne le premier objectif, une méthodologie pour évaluer la fiabilité du cluster a été proposée. Cette méthodologie emploie une méthode analytique déjà existante pour évaluer la fiabilité des circuits logiques combinatoires. La même méthode est utilisée pour identifier les blocs les plus éligibles au durcissement. Quant au deuxième objectif, des techniques de durcissement ont été proposées aux niveaux multiplexeur et transistor. Au niveau multiplexeur, deux solutions de durcissement ont été présentées. La première solution a recours à la redondance spatiale et concerne la structure du bloc logique. Une nouvelle architecture de BLE baptisée « Butterfly » est introduite. Elle a été comparée avec d'autres architectures de BLE en termes de fiabilité et de surcoût. La deuxième solution de durcissement est une technique dite « sans redondance ». Elle est basée sur une synthèse intelligente qui consiste à chercher la structure la plus fiable parmi toutes celles proposées dans la librairie du fondeur, avant d'utiliser directement de la redondance. Ensuite, au niveau transistor, de nouvelles architectures de multiplexeur, à sortie unique ou différentielles, ont été proposées. Elles ont été comparées à d'autres assemblages différents de transistors, selon des métriques de conception appropriées. / As feature sizes scale down to nano-design level, electronic devices have become smaller, more performant, less power-onsuming, but also less reliable. Indeed, reliability has arisen as a serious challenge in nowadays’ microelectronics industry and as an important design criterion, along with area, performance and power consumption. For instance, physical defects due to imperfections in the manufacturing process have been observed more frequently, impacting the yield. Besides, nanometric circuits have become more vulnerable during their lifetime to ionizing radiation which causes transient faults. Both manufacturing defects and transient faults contribute to decreasing reliability of integrated circuits. When moving to a new technology node, Field Programmable Gate Arrays (FPGAs) are the first coming into the market, thanks to their low development and Non-Recurring Engineering (NRE) costs and their flexibility to be used for any application. FPGAs have especially attractive characteristics for space and avionic applications, where reconfigurability, high performance and low-power consumption can be fruitfully used to develop innovative systems. However, missions take place in a harsh environment, rich in radiation, which can induce soft errors within electronic devices. This shows the importance of FPGA reliability as a design criterion in safety and critical applications. Most of commercial FPGAs have a mesh architecture and their logic blocks are gathered into clusters. Therefore, this thesis deals with the fault tolerance of basic blocks (clusters and switch boxes) in a mesh of clusters FPGA. These blocks are mainly made up of multiplexers. In order to improve their reliability, it is imperative to be able to assess it first, then select the proper hardening approach according to the available budget. So, this is the main outline in which this thesis is conceived. Its goals are twofold: (a) analyze the fault tolerance of the basic blocks in a mesh of clusters FPGA, and point out the most vulnerable components (b) propose hardening schemes at different granularity levels, depending on the hardening budget. As far as the first goal is concerned, a methodology to evaluate the reliability of the cluster is proposed. This methodology uses an existent analytical method for reliability computation of combinational circuits. The same method is employed to identify the worthiest components to be hardened. Regarding the second goal, hardening techniques are proposed at both multiplexer and transistor levels. At multiplexer level, two hardening solutions are presented. The first solution resorts to spacial redundancy and concerns the logic block structure. A novel Configurable Logic Block (CLB) architecture baptized Butterfly is introduced. It is compared with other hardened CLB architectures in terms of reliability and cost penalties. The second hardening solution is a redundanceless scheme. It is based on a “smart” synthesis that consists in seeking the most reliable design in a given founder library, instead of directly using a redundant solution. Then, at transistor level, new single-ended and dual-rail multiplexer architectures are proposed. They are compared to different other transistor structures, according to suitable design metrics.
|
48 |
An investigation and design of an infrared radiation heat profile controller /Adonis, Marcus Leroy. January 1900 (has links)
Thesis (MTech (Electrical Engineering))--Peninsula Technikon, 2002. / Word processed copy. Summary in English. Includes bibliographical references (p. 115-119). Also available online.
|
49 |
Design of an FPGA based parallel architecture processor for displaying CSG volumes and surfacesCevik, Ulus January 1996 (has links)
No description available.
|
50 |
Genetic programming in hardwareMartin, Peter N. January 2003 (has links)
No description available.
|
Page generated in 0.064 seconds