Thesis (M.S.)--University of Missouri-Columbia, 2004. / Typescript. Includes bibliographical references (leaf 54). Also available on the Internet.

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Approved for public release; distribution is unlimited / The space environment has unique hazards that force electronic systems designers to use different techniques to build their systems. Radiation can cause Single Event Upsets (SEUs) which can cause state changes in satellite systems. Mitigation techniques have been developed to either prevent or recover from these upsets when they occur. At the same time, modifying on-orbit systems is difficult in a hardwired electronic system. Finding an alternative to either working around a mistake or having to keep the same generation of technology for years is important to the space community. Newer programmable logic devices such as Field Programmable Gate Arrays (FPGAs) allow for emulation of complex logic circuits, such as microprocessors. FPGAs can be repro-grammed as necessary, to account for errors in design, or upgrades in software logic circuits. In an effort to provide one solution for both of these issues, this research was undertaken. The Configurable Fault Tolerant Processor (CFTP) emulates three identical processors, using Triple Modular Redundancy (TMR) to mitigate SEUs on a radiation tolerant FPGA. With the reconfigurable capabilities of FPGA technology, as newer processors can be emulated, these new configurations can be uploaded to the satellite as software code, thereby actually upgrading the processor in flight. This research used a 16-bit Reduced Instruction Set Computer (RISC) processor as its cores. This thesis describes how the Harvard architecture of the processor is interfaced with the Von Neumann architecture of the memory. It also develops the process by which errors are detected and corrected, as well as recorded. The end result is a design simulation ready for implementation on an FPGA. / Lieutenant, United States Navy

Thesis (Ph.D.)--University of Delaware, 2006. / Principal faculty advisor: Dennis W. Prather, Dept. of Electrical and Computer Engineering. Includes bibliographical references.

As the level of integrated circuit (IC) complexity continues to increase, the post-silicon validation stage is becoming a large component of the overall development cost. To address this, we propose a reconfigurable post-silicon debug infrastructure that enhances the post-silicon validation process by enabling the observation and control of signals that are internal to the manufactured device. The infrastructure is composed of dedicated programmable logic and programmable access networks. Our reconfigurable infrastructure enables not only the diagnoses of bugs; it also allows the detection and potential correction of errors in normal operation. In this thesis we describe the architecture, implementation and operation of our new infrastructure. Furthermore, we identify and address three key challenges arising from the implementation of this infrastructure. Our results demonstrate that it is possible to implement an effective reconfigurable post-silicon infrastructure that is able to observe and control circuits operating at full speed, with an area overhead of between 5% and 10% for many of our target ICs.

3D graphics pipeline can be divided into two subsystems: geometry subsystem and rendering subsystem. Hardware implementation of the transformation and lighting in the geometric subsystem can be divided into two categories, fixed function pipeline and programmable vertex shader. This thesis proposes a programmable vertex shader design based on OpenGL ES 2.0 specification. We start from the design of instruction set and use a multiplier-accumulator (MAC)-based SIMD (Single-Instruction Multiple-Data) structure. The vertex shader supports both floating-point and fixed-point operations of both scalar and vector formats. In addition, the special function unit for calculation of complicated functions is also integrated in the vertex shader. Besides, we also make out best to minimize the cost, power ,and delay during the entire design process.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 2003. / Thesis advisor(s): Herschel H. Loomis, Alan A. Ross. Includes bibliographical references (p. 117). Also available online.

Due to their high potential performance and reduced energy and power consumption, field-programmable gate arrays (FPGAs) are widely used as accelerators for today’s computationally intensive applications. These applications use advanced algorithms more sophisticated than ever before. The high design complexity along with fast development process challenges the traditional FPGA design methodology using hardware description languages. High-level synthesis accelerates design implementation by raising the level of design abstraction beyond register transfer level. This dissertation work develops a highly energy-efficient FPGA high-level synthesis tool, ArchSyn, using an application-specific coarse-grain architecture as an intermediate synthesis step. ArchSyn provides rapid and energy-efficient compilation of dataflow graphs (DFGs) on FPGAs by scheduling the dataflow operations on an array of directly connected simple configurable processing elements (CPEs). Each CPE in the array performs primitive compute operations according to a small local sequencer at each cycle. Data are communicated via multi-hop routing within the direct interconnect network. The scheduler schedules each compute operation of the DFG obtained from the high-level design to execute on a particular hardware CPE at a particular cycle. It also determines the communication schedule of the intermediate data among the producing and consuming CPEs, optionally buffering them with distributed memory along the path. As such, the lengthy process of synthesizing a full custom hardware design on FPGA is reduced to a scheduling and mapping process. By restricting the fine-grain programmability into a coarse grain processor network scheduling problem, the compilation time can be improved substantially, thereby improving the overall productivity of the designer. Furthermore, taking advantage of the programmability of FPGAs, the effect of the array interconnect architecture on the energy-efficiency of the resulting system is studied. By altering the array configuration, the data communication scheme among the CPEs must also be changed. This has a net effect on both the energy consumption spent on data movement as well as on the overall compute performance. It is shown that by using array topology that is customized to the input DFG, up to 28% improvement in energy-efficiency could be achieved. An exploratory framework based on a genetic algorithm was developed that allows us to obtain such application-specific connection network. Such degree of customization is possible only with the programmability of FPGAs. Moreover, such topology adaptation can be achieved rapidly as only routings between a fixed set of pre-placed CPEs are required. Implementations using ArchSyn and an existing FPGA compilation tool xPilot were compared. ArchSyn gave a 2X better energy consumption and a 11X better energy-delay product for computation with very regular and simple data dependency. For computation with irregular data dependency, the energy consumption and energy-delay product improvement was 9.6X and 199X. / published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy