3D graphics pipeline can be divided into two subsystems: geometry subsystem and rendering subsystem. Hardware implementation of the transformation and lighting in the geometric subsystem can be divided into two categories, fixed function pipeline and programmable vertex shader. This thesis proposes a programmable vertex shader design based on OpenGL ES 2.0 specification. We start from the design of instruction set and use a multiplier-accumulator (MAC)-based SIMD (Single-Instruction Multiple-Data) structure. The vertex shader supports both floating-point and fixed-point operations of both scalar and vector formats. In addition, the special function unit for calculation of complicated functions is also integrated in the vertex shader. Besides, we also make out best to minimize the cost, power ,and delay during the entire design process.

This thesis focuses on efficient design of a vertex shader for per-vertex operations such as Transformation and Lighting in the OpenGL ES 2.0 graphics pipeline. The vertex shader performs these complex operations using logarithmic number system, and makes partial optimization for the hardware area based on the accuracy requirement of half-precision floating-point. The vertex shader design emphasizes low cost, and is well suited to low-accuracy embedded applications. The vertex shader is an SIMD (Single-Instruction-Multiple-Data) design with customized instruction set that allows users to write efficient vertex shader programs.

OpenGL ES 2.0 programmable 3D graphics pipeline is the current new standard for embedded graphics processor designs. The programmable vertex shader replaces the geometry operations in the previous fixed-function graphics pipeline and provides more flexible APIs for more realistic animation effects. In this thesis, we introduce the OpenGL ES 2.0 specification, and the design of programmable vertex shader architecture and instruction set. In particular, we focus on the integration issues encountered when the vertex shader is integrated with other hardware components and software during the entire SoC design, and verify the vertex shader on FPGA with demonstration.

With technology increasingly and the needs of high performance and multiple functionalities, power dissipation has be a bottleneck in microprocessors. And clock power is the most percentage of total power dissipation. In our thesis, we will provide an effective clock gating methodology that has not more overhead possibly to decrease total power dissipations based on SIMD 3D vertex shader. Except for classify all instructions according the instruction flow, we also consider the relationship of pipeline stage and are based on register bank to control execution units more flexibility. Using clock gating not only can decrease clock power, but also decrease the power of hardware modules succeed the registers with clock gating that be controlled. In our thesis, we will analysis which clock gating version is suitable because there is not definitely to disable the clock of all pipeline registers of all pipeline stages and hold all opportunities that can disable the clock. We will explain on experimental results and show the final low power version. With experimental results, the clock gating methodology that we bring can decrease almost 30% power with increase less than 2% area. And collection of instruction schedule algorithm for high performance that can decrease 41% energy at most. In new version of four vertexes execute sequentially, using clock gating can also decrease almost 10% power dissipation. And collection of instruction schedule algorithm for this version not only has better performance result but also can decrease 16% energy at most.

Vertex shader, one of the core parts in 3D graphics systems, is to speed up the operations of coordinate transformation and lighting in 3D graphics pipeline, and vector ALU is the key part of a vertex shader. This thesis proposes several unified architectures that integrate the floating-point vector arithmetic unit and special function unit in order to share some hardware resource. We propose three different architectures for the design of the unified vector ALU. The first architecture includes a single-instruction-multiple-data (SIMD) vector arithmetic unit, and uses table-based method with first-order approximation to calculate some special functions. The second architecture use higher-order approximation to reduce the table sizes and share the floating-point multipliers in the SIMD vector unit. The proposed third architecture has two copies of hardware that can compute two dot-product operations in parallel and thus increase the throughput of the matrix computation by a factor of two. Furthermore, the two dot-product units can be used to perform the interpolation for special function calculation.

In computer graphics technique, the 3D graphic pipeline flow has two processing modules: Geometry module and Rendering module. The geometry module supports vertex coordinate transformation, vertex lighting computation, backface-culling, pre-clipping, and clipping functions. Clipping module clips the outside part of objects by view volume boundaries. Adding clipping module into geometry module will make 3D graphics pipeline flow more efficiency. Due to the sequential parsing nature of clipping, it causes the challenges to implement clipping function in hardware design. This paper implements a dual-path clipping engine placed after the Vertex Shader in geometry module and supports OpenGL-ES 2.0 specification. With the clipping engine, it reduces the unnecessary operations in 3D graphics pipeline flow and makes the performance efficient. The pipelined and shared hardware design is proposed to improve the area cost and throughput of the interpolation operation in clipping engine. The two vertices in/out clipping method is proposed in this paper. Users have more different choices of clipping algorithms for hardware implementation with respect to the performance and hardware limitation.

Modern graphics accelerators have embedded programmable components in the form of vertex and fragment shading units. Current APIs permit specification of the programs for these components using an assembly-language level interface. Compilers for high-level shading languages are available but these read in an external string specification, which can be inconvenient. It is possible, using standard C++, to define an embedded high-level shading language. Such a language can be nearly indistinguishable from a special-purpose shading language, yet permits more direct interaction with the specification of textures and parameters, simplifies implementation, and enables on-the-fly generation, manipulation, and specification of shader programs. An embedded shading language also permits the lifting of C++ host language type, modularity, and scoping constructs into the shading language without any additional implementation effort.

Modern graphics accelerators have embedded programmable components in the form of vertex and fragment shading units. Current APIs permit specification of the programs for these components using an assembly-language level interface. Compilers for high-level shading languages are available but these read in an external string specification, which can be inconvenient. It is possible, using standard C++, to define an embedded high-level shading language. Such a language can be nearly indistinguishable from a special-purpose shading language, yet permits more direct interaction with the specification of textures and parameters, simplifies implementation, and enables on-the-fly generation, manipulation, and specification of shader programs. An embedded shading language also permits the lifting of C++ host language type, modularity, and scoping constructs into the shading language without any additional implementation effort.

Asynchronous bus interface units to AMBA AHB are designed so that an OpenGL ES 2.0 vertex shader can communicate with other hardware units via AHB bus under different working frequencies. The first design is to directly implement an asynchronous AHB wrapper for the vertex shader. The other two designs are based on Open Core Protocol (OCP) to allow for more flexibility. The hardware intellectual property (IP), vertex shader in this thesis, to OCP asynchronous unit is designed so that the IP can be developed independently with different bus protocols as long as the OCP-to-bus interface is provided for a particular bus protocol. With the help of asynchronous IP-to-OCP and OCP-to-AHB interface units, the vertex shader IP can operate at different frequencies from the AHB bus. Furthermore, the same vertex shader (VS) can be connected to other bus protocol (such as AXI) of different frequencies if the OCP-to-AXI interface is provided because the the asynchronous VS-to-OCP have been designed in this thesis.

Graphics processing unit (GPU) designs usually adopts various computer architecture techniques to boost the computation speed, including single-instruction multiple data (SIMD), very-long-instruction word (VLIW), multi-threading, and/or multi-core. In OpenGL ES 2.0, user programmable vertex shader (VS) hardware unit can be designed using vectored SIMD computation unit so that it can efficiently compute the matrix-vector multiplication, one of the key operations in vertex transformation. Recently, high-performance GPU, such as Telsa series from nVidia, is designed with many-core architectures with each core responsible for scalar operations. The intention is to allow for efficient execution of general-purpose computations in addition to the specialized graphics computations. In this thesis, we design a scalar-based multi-threaded GPU design that is composed of four scalar processors, one special-function unit, and can execute multi-threaded instructions. We use the example of vertex transformation to demonstrate execution efficiency of the scalar-based multi-threaded GPU. We also make comparison with the vector-based SIMD GPU.